High fosc/fT 毫米波CMOS壓控振盪器

Abstract

近年來，因為不需使用執照的7 GHz頻寬以及許多良機的可行性，對60-GHz 應用的RFIC設計，越來越吸引全世界IC設計的興趣。此論文提出一個積體化的，應用於60 GHz UWB 的49 GHz的壓控振盪器。這個壓控振盪器利用最大截止頻率，fT ，是60 GHz的商業用0.18μm製程來實現。為了功率考量，電路偏壓在截止頻率約為55 GHz，導致VCO fosc/fT有接近0.9的高比值。VCO電路的核心部分使用了90 μm × 120 μm的晶片面積以及消耗4 mW的功率。LC電路使用線型電感以及NMOS的變容器。量測到的相位雜訊在偏移中心頻率1MHz時是 -96 dBc/Hz，使得電路與最近已發表振盪基頻在40 GHz以上，甚至使用更先進製程的CMOS VCO比較，擁有最好的-184 dBc/Hz的FOM值。 在第一章中，我們簡短介紹目前60 GHz不需使用執照的頻帶以及提出射頻前端的架構。在第二章裡，一些振盪器的基本概念以及架構，將作一些闡述。第三章介紹熱雜訊以及閃爍雜訊對相位雜訊造成的影響。第四章是模擬與量測的結果，最後是論文的總結。

Recently the RFIC designed for 60 GHz applications has attracted growing interest worldwide because of the availability of the unlicensed 7 GHz bandwidth and numerous opportunities. An integrated 1-V, 49 GHz CMOS voltage-controlled-oscillator (VCO) is developed for the emerging 60-GHz UWB applications is presented in this paper. The VCO implemented in a commercial 0.18μm CMOS technology of which the maximum cut-off frequency, fT, is 60 GHz. For power consideration, the circuit biased at the cut-off frequency is about 55 GHz which lead to the VCO achieves a high fosc/fT approximate to 0.9. The core VCO circuitry consumes 4 mW of power and occupies only 90 μm × 120 μm of the silicon estate. The high quality-factor line inductors and NMOS varactors are used to construct the LC-resonators. The measured phase noise at 1 MHz offset from 49 GHz is -96 dBc/Hz. The low phase noise combined with low power consumption leads to an excellent Figure-of-Merit (FOM) of -184 dBc/Hz, which is the best of the fundamental CMOS VCOs above 40GHz. In Chapter 1, the introduction of the 60 GHz applications and proposed RF front-end receiver architecture are presented. The basic concepts and topologies of the oscillators are expounded in Chapter 2. The VCO phase noises caused by thermal and flicker noise are present in Chapter 3. The simulation and measurement results are shown in Chapter 4, followed by the conclusion.