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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/34665完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Po-Lin Wu | en |
| dc.contributor.author | 吳柏霖 | zh_TW |
| dc.date.accessioned | 2021-06-13T06:21:19Z | - |
| dc.date.available | 2007-02-06 | |
| dc.date.copyright | 2006-02-06 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-01-24 | |
| dc.identifier.citation | [1] E. J. Marinissen , Y. Zorian, and S. Dey, “Testing Embedded Core-based System Chips “, in Proc. Int. Test Conf. (ITC), pp. 130-143, 1998.
[2] E. J. Marinissen , Y. Zorian, and S. Dey, “Testing Embedded Core-based System Chips “, Computer , vol. 32 , no 6, pp. 52-60, 1999. [3] T. Taylor, E. J. Marinissen, Y. Zorian, and L. Whetsel, “Towards a Standard for Embedded Core Test: An Example”, in Proc. Int. Test Conf. (ITC), pp. 616-627, 1999. [4] L. Whetsel , R. Kupar , F. Dasilva , Y. Zorian , “Overview of the IEEE P1500 standard”, in Proc. Int. Test Conf. (ITC) , pp. 887-889, 2003. [5] IEEE 1500 Working Group, ”IEEE P1500 Working Group on a Standard for Embedded Core Test (SECT)”, http://grouper.ieee.org/groups/1500/, 2002. [6] Y. Zorian , “Test Requirements for Embedded Core-based Systems and IEEE P1500”, in Proc. Int. Test Conf. (ITC) , pp. 191-199 , 1997. [7] Y. Zorian, “System-Chip Test Strategies”, in Proc. IEEE/ACM Design Automation Conf. (DAC), pp. 752-757 , 1998. [8] E. Marinissen , R. Kupar , M. Lousberg , T. Mclaurin , M. Ricchetti , and Y. Zorian, “On IEEE P1500’s standard for embedded core test”, J. Electronic Testing Theory and Application , vol. 18 , no. 4-5 , pp. 365-383 , Aug. –Oct. 2002. [9] E. J. Mcluskey, S. Mitra, and S. Makar, ”Design for Testability and testing of IEEE 1149.1 TAP controller”, Proc. IEEE VLSI Test Symp.(VTS), pp. 247-252, 2002. [10] T. McLaurin and S. Ghosh, “ETM10 Incorporates Hardware Segment of IEEE 1500”, IEEE Design and Test of Computers, pp. 6-11, 2002. [11] Synopsys, “TetraMax User Guide”, Synopsys user’s manual, 2004. [12] C. -W Chou, “A Hierarchical Test Access Mechanism for SOC and the Automatic Test Development Flow”, National Tsing Hua Univ. Master Thesis, 2001. [13] Synopsys, “SoCBIST SoCTest User Guide”, Synopsys user’s manual, 2003 [14] C. -W. Wu, “Core-based SOC Testing”, VLSI Testing and Design for Testability (Ⅱ), course handouts, 2002. [15] J. -F. Li and C. -S. Wu, “Design-for-Testability and Testing of P1500 Test Wrapper”, VLSI Design/CAD symposium, pp. 254-257, 2005. [16] Synopsys, “IEEE Standard Test Access Port and Boundary-Scan Architecture”, Synopsys user’s manual, 1990. [17] M. -H. Chiu and C. -M. Li, “Jump Scan: A DFT Technique for Low Power Testing” VLSI Test Symposium (VTS), pp. 277-282, 2005. [18] R. Dabholkar, V. Chakravarty , and S. Reddy, “Techniques for Reducing Power Dissipation During Test Application in Full Scan Circuits”, IEEE Trans. Computer-Added Design, vol. 17, no 12, pp 1325-1333 Dec. 1998,. [19] Synopsys, ”Power Compiler User Guide ”, Synopsys user’s manual, 2005. [20] Y. -T Liao, “A Two-Level Test Data Compression and Test Time Reduction Technique for SOC”, National Taiwan Univ. Master thesis, 2005. [21] IEEE P1500 CTL Working Group, “P1450.6 IEEE Standard for the Core Test Language (CTL)”, IEEE P1500 CTL user’s manual, 2003. [22] IEEE P1450.1 Working Group, “P1450.1 IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data Design Extension”, IEEE P1450.1 Working-Draft 14, 2002. [23] C. -M. Li, 'A Design for Testability Technique for Low Power Delay Fault Testing', IEICE Transactions on Electronics, v E87-C, n4, pp. 621-628, April, 2004. [24] R. Sankaralingam, B. Pouya and N. A. Touba, 'Reducing Power Dissipation During Test Using Scan Chain Disable', Proc. VLSI Test Symp.(VTS), pp. 337-342, 2002. [25] Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Design”, Proc. 11th IEEE VLSI Test Symp.(VTS), pp. 4-9, 1993. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/34665 | - |
| dc.description.abstract | 本論文實作了可以將核心電路自動包覆IEEE 1500標準封套與自動驗證之測試樣板產生器。透過此工具自動產生之測試樣板可支援單一測試圖樣(one-pattern test)與雙測試圖樣(two-pattern test)兩種測試方式，並提供了位移與強迫等測試圖樣輸入方式。在雙測試圖樣測試方面，我們提出了一種雙暫存器封套單元設計以及相對的測試程序，WBRTest。透過此測試程序，可使封套達成100%之錯誤涵蓋率。我們也對前版之封套編譯器作了相關之修正。除了驗證之外，自動化產生的測試樣板也能估算核心在不同測試模式測試圖樣輸入方式以及封套單元設計之下之模擬功率消耗。 | zh_TW |
| dc.description.abstract | In this thesis, an automatic testbench generator for testing IEEE 1500 wrapped cores is implemented. The generated testbench is flexible for testing wrapped cores in either one-pattern or two-pattern test applications. A two-register wrapper cell is also proposed for two-pattern test. Corresponding test sequence, WBRTest, guarantees 100% fault coverage for wrapper cells. Modification of original wrapper compiler is completed for the dedicated wrapper cell architecture and test sequence. Additional function of the testbench generator to calculate power consumption of a wrapped core is also added. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T06:21:19Z (GMT). No. of bitstreams: 1 ntu-95-R92943082-1.pdf: 620891 bytes, checksum: 6ec9d775d60b071b6bb5107001e206a8 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | 摘要………………………………………………………………………………..I
Abstract…………………………………………………………………………...II 目錄 III 列圖目錄 VI 列表目錄 IX 第一章 緒論 1 1.1 論文背景與動機 1 1.2 論文貢獻 2 1.3 論文組織 5 第二章 IEEE 1500標準與封套產生 6 2.1 IEEE 1500 標準介紹 6 2.1.1 IEEE 1500 封套 6 2.1.2 封套單元(wrapper cell) 10 2.1.3 輸入端封套單元(Input Wrapper Boundary Cell，IWBC)與 輸出端封套單元(Output Wrapper Boundary Cell，OWBC) 11 2.1.4 核心測試語言(Core Test Language，CTL) 12 2.2 自動化封套編譯器(Wrapper Compiler) 14 2.2.1 封套單元 14 2.2.2 指令暫存器 16 2.2.3 指令解碼器 16 2.3 雙暫存器封套單元設計 18 2.4 封套暫存器測試模式(WBRTest mode) 20 2.4.1 封套暫存器測試運作程序 20 2.4.2 封套暫存器測試之錯誤涵蓋率(Fault Coverage) 24 2.4.3 指令暫存器與指令解碼器之錯誤涵蓋率 28 2.5 其他雙暫存器封套單元設計 29 第三章 IEEE 1500測試封套之驗證 32 3.1 封套測試模式 33 3.1.1 封套核心內部測試模式(WCORETEST) 34 3.1.2 封套外部測試模式(WEXTESTS) 37 3.1.3 封套旁通測試模式(WBYPASS) 41 3.2 有封套核心之自動化測試樣板產生器之實現 44 3.2.1 自動化封套測試樣板產生器工作介面與使用流程 45 3.2.2 自動化封套測試樣板產生器之組成區塊 46 3.3 單一暫存器封套單元設計(1-Register WBC)之驗證 49 3.3.1 單一黏著錯誤模型測試圖樣驗證 49 3.3.2 單一黏著錯誤模型位移/強迫/位移-強迫輸入模式測試樣板產生器 50 3.3.3 位移輸入(shift-in)模式 50 3.3.4 強迫輸入(force-in)模式 53 3.3.5 位移-強迫(shift-force)輸入模式 54 3.3.6 轉換錯誤模型 55 3.3.7 單一暫存器封套單元設計之轉換錯誤模型測試樣板產生 58 3.4 雙暫存器封套單元設計(two-register WBC)之驗證 61 3.4.1 單一黏著錯誤模型之驗證 62 3.4.2 轉換錯誤模型LOS測試方式之驗證 63 3.4.3 轉換錯誤模型LOC測試方式之驗證 65 3.5 自動化測試樣板產生之困難與解決方式 66 第四章 核心模擬功率計算工具 69 4.1 功率計算工具PowerCompiler 69 4.1.1 測試功率 69 4.1.2 功率之組成與計算 70 4.1.3 閘層級模擬與SAIF檔案 71 4.2 程式介面語言(Program Interface Language，PLI) 73 4.3 模擬功率計算底稿 77 4.4 功率比較 78 第五章 實驗結果 79 5.1 模擬功率消耗 79 5.1.1 目標電路 79 5.1.2 無封套電路之功率消耗 80 5.1.3 單一暫存器封套電路之功率消耗 82 5.1.4 雙暫存器封套電路之功率消耗 83 5.1.5 功率比較 85 5.2 模擬CPU時間 86 5.2.1 無封套電路之模擬CPU時間 87 5.2.2 單一暫存器封套電路之模擬CPU時間 88 5.2.3 雙暫存器封套電路之模擬CPU時間 89 5.2.4 模擬CPU時間比較 90 5.3 合成面積 91 第六章 結論與未來展望 93 參考資料 96 | |
| dc.language.iso | zh-TW | |
| dc.subject | 功率 | zh_TW |
| dc.subject | 驗證 | zh_TW |
| dc.subject | 封套 | zh_TW |
| dc.subject | validation | en |
| dc.subject | wrapper | en |
| dc.subject | power | en |
| dc.title | IEEE 1500標準測試封套產生和驗證及功率預估自動化工具之實現 | zh_TW |
| dc.title | Implementation of an IEEE 1500 Test Wrapper Generation, Validation and Power Estimation Tool | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃俊郎(Jiun-Lang Huang),饒建奇(Jiann-Chyi Rau) | |
| dc.subject.keyword | 封套,驗證,功率, | zh_TW |
| dc.subject.keyword | wrapper,validation,power, | en |
| dc.relation.page | 99 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-01-25 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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