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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Yu-Long Kao | en |
| dc.contributor.author | 高玉龍 | zh_TW |
| dc.date.accessioned | 2021-06-13T05:50:47Z | - |
| dc.date.available | 2006-07-10 | |
| dc.date.copyright | 2006-07-10 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-06 | |
| dc.identifier.citation | [Edirisooriya 95] S. Edirisooriya, and G. Edirisooriya, “Diagnosis of Scan Path Failures,” Proc. IEEE VLSI Test Symp., pp. 250-255, 1995.
[Guo 01] R. Guo, and S. Venkataranman, “A Technique for Fault Diagnosis of Defects in Scan Chains,” Proc. IEEE Int’l Test Conf., pp. 268-277, 2001. [Guo 02] R. Guo, and S. Venkataranman , “A New Technique for Scan Chain Failure Diagnosis,” Proc. Int’l Symp. Testing and Failure Analysis, pp. 723-732, 2002. [Hirase 99] J. Hirase, N. Shindou, and K. Akahori, “Scan Chain Diagnosis Using IDDQ Current Measurement,” Proc. Asian Test Symp. pp. 153-157, 1999. [Huang 03] Y. Huang, W.-T. Cheng, S. M. Reddy, C.-J. Hsieh, and Y.-T. Hung, “Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault,” Proc. IEEE Int’l Test Conf., pp. 319-327, 2003. [Huang 05] Y. Huang, W.-T. Cheng, and J. Rajski, “Compressed Pattern Diagnosis for Scan Chain Failures,” Proc. IEEE Int’l Test Conf., paper 30.3, 2005. [Kruseman 04] B. Kruseman, A. Majhi, C. Hora, S. Eichenberger, J. Meirlevede, “Systematic Defects in Deep Sub-Micron Technologies,” Proc. IEEE Int’l. Test Conf., pp. 290-298, 2004. [Kundu 94] S. Kundu, “Diagnosing Scan Chain Faults,” IEEE Trans. VLSI Syst., pp. 512-516, 1994. [Lee 91] H. K. Lee and D. S. Ha, “On the Generation of Test Patterns of Combinational Circuits,” Technical Report, No 12-93, Dept. of Electrical Eng. Virginia Polytechnic Institute and State University, 1991. [Li 05a] J. C.-M. Li, “Diagnosis of Single stuck-at Faults and Multiple Timing Faults in Scan Chains, “ IEEE Trans. on VLSI Systems, Vol.13, No. 6, June, 2005, pp. 708-718. [Li 05b] J. C.-M. Li, “Diagnosis of Multiple Hold-time and Setup-time Faults in Scan Chains,” IEEE Trans. on Computers, Vol. 54, No. 11, 2005, pp. 1467-1472. [Narayanan 97] S. Narayanan and A. Das, “An Efficient Scheme to Diagnose Scan Chains,” Proc. IEEE Int’l Test Conf., pp.704-713, 1997. [Nigh 98] P. Nigh, D. Vallett, A. Patel and et. al., “Failure Analysis of Timing and IDDq Failures from the SEMATECH Test Methods Experiment,“ Proc. IEEE Int’l. Test Conf., pp.43-52 , 1998. [Pradhan 86] D. K. Pradhan (editor), Fault Tolerant Computing: Theory and Techniques, Prentice Hall, 1986. [Schafer 92] J. Schafer, F. Policastri and R Mcnulty, “Partner SRLs for Improved Shift Register Diagnostics,” Proc. IEEE VLSI Test Symp., pp. 198-201, 1992. [Song 04] P. Song, F. Stellari, T. Xia, and A. Weger, “A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current,” Proc. IEEE Int’l. Test Conf., pp. 140-147, 2004. [Stanley 01] K. Stanley, “High-Accuracy Flush-and-scan Software Diagnostic,” IEEE Des. Test. Comput., pp. 56-62, Nov-Dec, 2001. [Wu 98] Y. Wu, “Diagnosis of Scan Chain Failures,” Int’l Symp. On Defect and Fault Tolerance in VLSI systems, pp. 217-222, 1998. [Yang 05] J.-S. Yang and S.-Y. Huang, “Quick Scan Chain Diagnosis Using Signal Profiling, “ Proc. Int’l Conf. on Computer Design, Oct. 2005. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33986 | - |
| dc.description.abstract | 本論文提出一種新的掃描鏈診斷技術可診斷掃描鏈上的七種單一錯誤，包括兩種黏著性錯誤及五種時間性錯誤。此技術實現跳躍模擬─一種新穎的平行模擬技術─此技術能快速找出錯誤分子的上邊界及下邊界。無論掃描鏈長度為何，跳躍模擬能將多次模擬一次完成，因此模擬時間相當短。此外，跳躍模擬藉由觀察被大多數診斷技術忽略的主要電路數據輸出及掃描鏈數據輸出來縮小錯誤分子的範圍。在ISCAS’89基準電路的實驗顯示，平均而言，跳躍模擬只需三個錯誤圖樣將錯誤分子範圍縮小至十個以下。當錯誤的資料被截短因為被測試機台記憶體限制時，此技術依然相當有效診斷電路。 | zh_TW |
| dc.description.abstract | This thesis presents a scan chain diagnosis technique to locate seven types of single faults in scan chains, including two single stuck-at faults and five single timing faults. This technique implements the Jump Simulation, a novel parallel simulation technique, to quickly search for the upper and lower bounds of the fault. Regardless of the scan chain length, Jump Simulation packs multiple simulations into one so the simulation time is short. In addition, Jump Simulation tightens the bounds by observing the primary outputs and scan outputs of good chains, which are ignored by most previous techniques. Experiments on ISCAS’89 benchmark circuits show that, on the average, only three failure patterns are needed to locate faults within ten scan cells. The proposed technique is still very effective when failure data is truncated due to limited ATE memory. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T05:50:47Z (GMT). No. of bitstreams: 1 ntu-95-R93943100-1.pdf: 833460 bytes, checksum: 8ec2f2a1132d514cc414ec577a080178 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | 摘要 I
Abstract II Table of Contents III List of Figures V List of Tables VII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Contributions 3 1.3 Organization 5 Chapter 2 Background 7 2.1 Scan Chain Fault Models 7 2.2 Determining Fault Model 10 2.3 Simulation Model 11 2.4 Past Research in Scan Chain Diagnosis 13 2.5 Comparison with Guo’s Technique 25 Chapter 3 Proposed Diagnosis Technique 30 3.1 Diagnosis Flow 30 3.2 Bounds Finder 31 3.2.1 Initialize UB/LB 33 3.2.2 UB Jump Simulation 34 3.2.3 Update UB 41 Update UB/LB 43 3.2.4 LB Jump Simulation 44 3.2.5 Update LB 47 3.3 Detailed Simulation and Match 49 Chapter 4 Software Implementation 50 4.1 Architecture of this Technique 50 4.2 Read Circuit 51 4.3 Read Scanpath 52 4.4 Read Pattern and Read Observed Outputs 53 4.5 Bounds Finder 55 4.5.1 Initialize UB/LB 56 4.5.2 Pattern Filler 57 4.5.3 Update UB/LB 61 4.6 Fault Simulation and Match 63 Chapter 5 Experimental results 65 5.1 Experimental Environment 65 5.2 Diagnosis Resolution 68 5.3 Number of Candidates 69 5.4 S10 and P10 71 Chapter 6 Discussions and Future work 74 6.1 Discussions 74 6.1.1 Intermittent Faults 74 6.1.2 Multiple System Clocks 74 6.1.3 Inversions in Scan Chains 75 6.2 Future work 77 Chapter 7 Summary 78 References 79 | |
| dc.language.iso | en | |
| dc.subject | 掃描鏈 | zh_TW |
| dc.subject | 錯誤診斷 | zh_TW |
| dc.subject | 跳躍 | zh_TW |
| dc.subject | diagnosis | en |
| dc.subject | jump simulation | en |
| dc.subject | scan chain | en |
| dc.title | 跳躍模擬：快速且精確之掃描鏈錯誤診斷技術 | zh_TW |
| dc.title | Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃鐘揚(Chung-Yang Huang),黃俊郎(Jiun-Lang Huang) | |
| dc.subject.keyword | 掃描鏈,錯誤診斷,跳躍, | zh_TW |
| dc.subject.keyword | scan chain,diagnosis,jump simulation, | en |
| dc.relation.page | 80 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-07-06 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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