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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33949完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭正邦 | |
| dc.contributor.author | Chia-Hung Lin | en |
| dc.contributor.author | 林家弘 | zh_TW |
| dc.date.accessioned | 2021-06-13T05:49:46Z | - |
| dc.date.available | 2006-07-14 | |
| dc.date.copyright | 2006-07-14 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-06 | |
| dc.identifier.citation | [1] J. B. Kuo and S. C. Lin, Low-Voltage SOI CMOS VLSI Devices and Circuits, New York: Wiley, 2001.
[2] C. Hobbs, H. Tseng, K. Reid, B. Taylor, L. Dip, L. Hebert, R. Garcia, R. Hegde, J. Grant, D. Gilmer, A. Franke, V. Dhandapani, M. Azrak, L. Prabhu, R. Rai, S. Bagchi, J. Conner, S. Backer, F. Dumbuya, B. Nguyen, and P. Tobin, “80nm poly-Si gate CMOS with HfO2 gate dielectric,” in IEDM Tech. Dig., 2001, pp. 651-654. [3] K. G. Anil, A. Veloso, S. Kubicek, T. Schram, E. Augendre, J. F. de Marneffe, K. Devriendt, A. Lauwers, S. Brus, K. Henson, and S. Biesemans, “Demonstration of fully Ni-silicided metal gates on HfO2 based high-k gate dielectrics as a candidate for low power applications,” in VLSI Symp. Tech. Dig., 2004, pp. 190-191. [4] A. Vandooren, S. Egley, M. Zavala, T. Stephens, L. Mathew, M. Rossow, A.Thean, A. Barr, Z. Shi, T. White, D. Pham, J. Conner, L. Prabhu, D. Triyoso, J. Schaeffer, D. Roan, B. Y. Nguyen, M. Orlowski, and J. Mogab, “50nm FD SOI CMOS technology with HfO2 gate dielectric,” IEEE Trans. Nanotechnol., vol. 2, no. 4, pp. 324-328, Dec. 2003. [5] A. Vandooren, A. Barr, L. Mathew, T. R. White, S. Egley, D. Pham, M. Zavala, S. Samavedam, J. Schaeffer, J. Conner, B. Y. Nguyen, B. E. White, Jr., M. K. Orlowski, and J. Mogab, “Fully-depleted SOI devices with TaSiN gate, HfO2 gate dielectric, and elevated source/drain extensions,” IEEE Electron Device Lett., vol. 24, no. 5, pp. 342-344, May 2003. [6] S. C. Lin and J. B. Kuo, “Modeling the fringing electric field effect on the threshold voltage of FD SOI NMOS devices with the LDD/sidewall oxide spacer structure,” IEEE Trans. Electron Devices, Vol. 50, no. 12, pp.2559-2564, Dec. 2003. [7] S. C. Lin and J. B. Kuo, “Fringing-induced barrier lowering(FIBL) effects of 100nm FD SOI NMOS devices with high permittivity gate dielectrics and LDD/sidewall oxide spacer,” in Proc. SOI, Oct. 2002, pp. 93-94. [8] G. C. Y. Yeap, S. Kirishnan, and M. R. Lin, “Fringing-induced barrier lowering(FIBL) in sub-100nm MOSFETs with high-k gate dielectrics,” Electron. Lett., vol. 34, no. 11, pp. 1150-1152, May 1998. [9] D. L. Kencke, W. Chen, H. Wang, S. Mudanai, Q. Ouyang, A. Tasch, and S. Banerjee, “Source-side barrier effects with very high-k dielectrics in 50nm Si MOSFETs,” in Proc. Device Research Conf. Dig., Jun. 1999, pp. 22-23. [10] N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, “Modeling of parasitic capacitances in deep submicrometer conventional and high-k dielectric MOS transistors,” IEEE Trans. Electron Devices, vol. 50, no. 4, pp.959-966, Apr. 2003. [11] N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, “The effect of high-k gate dielectrics on deep submicrometer CMOS device and circuit performance,” IEEE Trans. Electron Devices, vol. 49, no. 5, pp. 826-831, May 2002. [12] MEDICI, User Guide, Version 2003.12, Synopsys, Mountain View, CA. [13] C. H. Choi, J. S. Goo, T. Y. Oh, Z. Yu, R. W. Dutton, A. Bayoumi, M. Cao, P. V. Voorde, D. Vook, and C. H. Diaz, “MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8nm),” IEEE Electron Device Lett., vol. 20, no. 6, pp. 292-294, Jun. 1999. [14] C. H. Choi, Y. Wu, J. S. Goo, Z. Yu, and R. W. Dutton, “Capacitance reconstruction from measured C-V in high leakage nitride/oxide MOS,” IEEE Trans. Electron Devices, vol. 47, no. 10, pp. 1843-1850, Oct. 2000. [15] Y. C. Yeo, T. J. King, and C. Hu, “MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations,” IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 1027-1035, Apr. 2003. [16] D. E. Ward and R. W. Dutton, “A charge-oriented model for MOS transistor capacitance,” IEEE J. Solid State Circuits, vol. SSC-13, no. 5, pp.703-708, Oct. 1978. [1] G. Timp et al., “Low-Leakage, Ultra-thin Gate Oxides for Extremely High Performance Sub-100nm nMOSFETs,” IEDM Digest, pp. 930-932, 1997. [2] H. Iwai and H. S. Momose, “Ultra-Thin Gate Oxides – Performance and Reliability,” IEDM Digest, pp. 163-166, 1998. [3] Y. Kim, C. Lim, C. D. Young, K. Matthews, J. Barnett, B. Foran, A. Agarwal, G. A. Brown, G. Bersuker, P. Zeitzoff, M. Gardner, R. W. Murto, L. Larwon, C. Metzner, S. Kher, and H. R. Huff, “Conventional Poly-Si Gate MOS – Transistors with a Novel, Ultra-thin Hf-oxide Layer,” Dig. Of Symp. VLSI Tech, pp. 167-168, 2003. [4] Y. C. Yeo, Q. Lu, W. C. Lee, T. J. King, C. Hu, X. Wang, X. Guo and T. P. Ma, “Direct Gate Leakage Current in Transistors with Ultrathin Silicon Nitride Gate Dielectric,” IEEE Electron Dev Lett, Vol. 21, No. 11, pp. 540-542, Nov. 2000. [5] B. Yu, H. Wang, C. Riccobene, Q. Xiang, and M. R. Lin, “Limits of Gate-Oxide Scaling in Nano-Transistors,” Digest of Symp. VLSI Tech, pp. 90-91, 2000. [6] W. K. Shih, E. X. Wang, S. Jallepalli, F. Leon, C. M. Maziar and A. F. Tasch, Jr., “Modeling Gate Leakage Current in NMOS Structures Due to Tunneling Through an Ultra-Thin Oxide,” Solid State Electronics, Vol. 42, No. 6, pp. 997-1006, 1998. [7] F. Lime, R. Clerc, G. Ghibaudo, G. Pananakakis, and G. Guegan, “Impact of Gate Tunneling Leakage on the Operation of NMOS Transistors with Ultra-Thin Gate Oxide,” Microelectronic Engineering, Vol. 59, pp. 119-125, 2001. [8] C. H. Choi, K. Y. Nam, and R. W. Dutton, “Impact of Gate Direct Tunneling Current on Circuit Performance,” IEEE Trans. Electron Devices, Vol. 48, No. 12, pp. 2823-2829, Dec. 2000. [9] D. E. Ward and R. Wu. Dutton, “A Charge-Oriented Model for MOS Transistor Capacitors,” IEEE J. Solid-State Circuits, Vol. 13, No. 5, pp. 703-708, 1978. [10] J. B. Kuo, R. W. Dutton and B.A. Wooley, “MOS Pass-Transistor Turn-off Transisent Analysis,” IEEE Trans. Electron Devices, Vol. 33, No. 10, pp. 1545-1555, Oct. 1986. [11] J. R. Burns, “Large-Signal Transit-Time Effects in the MOS Transistors,” RCA Rev., pp. 15-35, March 1969. [12] H. C. Chow, W. S. Feng, and J. B. Kuo, “An Improved Analytical Short-Channel MOSFET Model Valid in All Regions of Operation for Analog/Digital Circuit Simulation,” IEEE Trans. Computer-Aided Design, Vol. 11, No. 12, pp.1522-1528, Dec. 1992. [13] K. F. Schuegraf and C. Hu, “Hole Injection SiO2 Breakdown Model for Very Low Voltage Lifetime Extrapolation,” IEEE Trans. Electron Devices, Vol. 42, No. 5, pp. 761-767, May 1995. [14] W. Lee and C. Hu, “Modeling CMOS Tunneling Currents Through Ultrathin Gate Oxide Due to Conduction and Valence Band Electron and Hole Tunneling,” IEEE Trans. Electron Devices, Vol. 48, No. 7, pp. 1366-1373, July 2001. [15] Y. Taur and T. H. Ning, “Fundamental of Modern VLSI Devices,” Cambridge Univ. Press, 1998. [16] P. K. Ko, “Hot-Electron Effects in MOSFETs,” PhD dissertation, Univ of California, Berkeley, June 1982. [17] C. H. Lin, J. B. Kuo, K. W. Su and S. Liu, “Partitioned Gate Tunneling Current Model Considering Distributed Effect for CMOS Devices with Ultrathin (1nm) Gate Oxide,” Electronics Letters, Vol. 42, No. 3, pp. 182-184, Feb. 2006. [18] Y. G. Chen, S. Y. Ma, J. B. Kuo, and R. W. Dutton, “An Analytical Drain Current Model Considering Both Electron and Lattice Temperatures Simultaneously for Deep Submicron Ultrathin SOI NMOS Devices with Self Heating,” IEEE Trans. Electron Devices, Vol. 42, No. 5, pp. 899-906, May 1995. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33949 | - |
| dc.description.abstract | 本篇論文研究金氧半場效電晶體元件的電容行為和閘極穿遂電流模型。第一章簡介high-k材料的重要性。第二章考慮垂直及邊緣電通密度效應，模擬高介電係數閘極氧化層全解離絕緣體上矽互補式金氧半奈米元件之電容行為，根據二維模擬的結果，在1.5nm氧化鉿（HfO2）閘極氧化層元件上看到一條獨特的兩個步階（two-step）電容曲線，我們歸因於垂直及邊緣電通密度效應所造成的。第三章考慮電流分佈效應，推導超薄閘極氧化層（1nm）n型金氧半元件閘極穿遂電流模型，此模型把電流分佈分成三個區間探討，經由實驗數據驗證後，對於長通道或短通道元件的閘極電流皆能做出準確的預測。對長通道元件而言，閘極穿遂電流主要由前飽和區域（pre-saturation region）主導。對短通道元件，操作在飽和區時，閘極電流有可能變為負值，這是因為靠近汲極處通道表面垂直電場反向的緣故。第四章為總結。 | zh_TW |
| dc.description.abstract | The thesis analyzes the capacitance behavior and gate tunneling current model of MOS devices. Chapter 1 introduces the importance of high-k materials applied to gate dielectrics. Chapter 2 discusses the gate capacitances behavior of nanometer FD SOI CMOS devices with HfO2 high-k gate dielectric considering vertical and fringing displacement effects using 2D simulation. Based on the 2D simulation results, a unique two-step CS(D)G/CGS versus VG curve could be identified for the device with the 1.5nm HfO2 gate dielectric due to the vertical and fringing displacement effects. Chapter 3 derives the partitoned gate tunneling current model for NMOS devices with an ultra-thin（1nm） gate oxide considering the distributed effects. As verified by the experimentally measured data, this partitioned gate tunneling current model based on the three segment approach provides an accurate prediction of the gate current for the device with a long or short channel. Chapter 4 is the conclusion of this research. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T05:49:46Z (GMT). No. of bitstreams: 1 ntu-95-R93943051-1.pdf: 1687013 bytes, checksum: 94f4a85431c12d526775acda7ef4a685 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | 1 簡介••••••••••••••••••••••••••••••1
2 考慮垂直及邊緣電通密度效應，模擬高介電係數閘極氧化層全解離絕緣體上矽互補式金氧半奈米元件之電容行為 2.1 摘要••••••••••••••••••••••••••••4 2.2 簡介••••••••••••••••••••••••••••5 2.3 電容行為••••••••••••••••••••••••••6 2.4 討論••••••••••••••••••••••••••••10 2.5 結論••••••••••••••••••••••••••••13 2.6 參考資料••••••••••••••••••••••••••13 3 考慮電流分佈效應之超薄閘極氧化層（1nm）n型金氧半元件閘極穿遂電流模型 3.1 摘要••••••••••••••••••••••••••••29 3.2 簡介••••••••••••••••••••••••••••30 3.3 模型推導••••••••••••••••••••••••••30 3.3.1 三極區•••••••••••••••••••••••31 3.3.2 飽和區•••••••••••••••••••••••34 3.4 模型驗證••••••••••••••••••••••••••39 3.5 討論••••••••••••••••••••••••••••41 3.6 總結••••••••••••••••••••••••••••42 3.7 參考資料••••••••••••••••••••••••••43 4 總結••••••••••••••••••••••••••••••56 | |
| dc.language.iso | zh-TW | |
| dc.subject | 穿遂電流 | zh_TW |
| dc.subject | 電容 | zh_TW |
| dc.subject | SOI | en |
| dc.subject | tunneling | en |
| dc.subject | capacitance | en |
| dc.title | 金氧半場效電晶體之電容行為及閘極穿遂電流模型分析 | zh_TW |
| dc.title | Modeling of MOSFET Devices : capacitance behavior analysis and gate tunneling current model | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林浩雄,賴飛羆,蘇哿暐 | |
| dc.subject.keyword | 電容,穿遂電流, | zh_TW |
| dc.subject.keyword | SOI,capacitance,tunneling, | en |
| dc.relation.page | 56 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-07-07 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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