後佈局階段考量良率提升之雙導通孔設計

Abstract

隨著積體電路技術進入奈米(nanometer)製程的時代，導通孔的開路 (via-open)缺陷是由於銅鍍(copper cladding)製程所造成首要電路失效中的一種。為了提升導通孔的良率以及可靠度，冗餘導通孔插入(redundant-viainsertion)是一項由晶圓代工廠高度推薦的技術。傳統上，雙導通孔插入(double-via insertion)都是在後佈局(post-layout)階段執行。在此論文中，我們提出了一個新式後佈局階段雙導通孔插入演算法，以達到較高的雙導通孔插入率。根據二分圖(bipartite graph)對集(matching)的公式轉換，我們發展了一個在三層繞線層(routing layer)以及堆疊導通孔(stack-via)的前提下，最佳的雙導通孔插入演算法；然後再將此最佳演算法延伸至可處理所有的實例。完善的實驗結果顯示，我們的方法不但顯著地降低了執行時間(running time)，並且也有效地提升了雙導通孔插入率。我們提出的演算法，不但雙導通孔插入率高達98.6%，並且與目前文獻中最新發展之雙導通孔插入演算法比較起來，總計的執行時間亦快了300倍。此外，與工業界的雙導通孔插入演算法比較起來，執行時間亦加速了125倍。由此可顯現出我們所提出的方法之優異的效率及性能。

As technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by foundries. Traditionally, double-via insertion is performed at the post-layout stage. In this thesis, based on a bipartite graph matching formulation, we develop an optimal post-layout double-via insertion algorithm for the cases with up to three routing layers and the stack-via structure, and then extend the algorithm to handle the general cases. Extensive experiments show that our methods significantly improve double-via insertion rates and running times. Compared with the state-of-the-art double-via insertion algorithm, our proposed algorithm can achieve a 98:6% double-via insertion rate with a 300X total runtime speedup. Also, our proposed algorithm can achieve a 98:5% double-via insertion rate with a 125X runtime speedup, compared with an industrial commercial tool.