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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
dc.contributor.author | Shing-Wei Chang | en |
dc.contributor.author | 張興維 | zh_TW |
dc.date.accessioned | 2021-06-13T04:40:35Z | - |
dc.date.available | 2006-07-24 | |
dc.date.copyright | 2006-07-24 | |
dc.date.issued | 2006 | |
dc.date.submitted | 2006-07-18 | |
dc.identifier.citation | [1] Y. Cai, B. Laquai, K. Luehman, “Jitter Testing for Gigabit Serial Communication Transceivers,” IEEE Design & Test of Computers, Volume 9, Issue 1, 2002, pp.64-74
[2] Y. Cai, S. A. Werner, G. J. Zhang, M. J. Olsen, R. D. Brink, “Jitter Testing for Multi-Gigabit Backplane SerDes,” ITC Proceedings, 2002, pp.700-709 [3] T. Yamaguchi, M. Soma, M. Ishida, H. Musha, L. Malarsie, “A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter,” ITC Proceedings, 2002, pp.717-725 [4] J. Wilstrup, “A Method of Serial Data Jitter Analysis Using One-shot Time Interval Measurement,” ITC Proceedings, 1998, pp.819-823 [5] S. Tabatabaei, M. Lee, F. Ben-Zeev, “Jitter Generation and Measurement for Test of Multi-Gbps Serial IO,” ITC Proceedings, 2004, pp.1313-1321 [6] B. Laquai, Y. Cai, “Testing Gigabit Multilane SerDes Interfaces with Passive Jitter Injection Filters,” ITC Proceedings, 2001, pp.297-305 [7] M. Lin, K. T. Cheng, J. Hsu, MC Sun, J. Chen, S. Lu, “Low-Cost Production-Oriented Testing for PCI-Express Interface,” International Mixed Signals Testing Workshop, 2005 [8] K. P. Li, “BIST Design for Jitter Injection of High Speed Transceivers,” Graduate Institute of Electronics Engineering, NTU, 2005 [9] Fibre Channel – Methodologies for Jitter and Signal Quality Specification – MJSQ, 2004 [10] Tektronix technology, “Jitter Generation Technique For Serializer-Deserializer Compliance Testing” [11] N. Ou, T. Farahmand, A. Kuo, S. Tabatabaei, A. Ivanov, “Jitter Models for the Design and Test of Gbps-Speed Serial Interconnect,” IEEE Design & Test of Computers, Volume 21, Issue 4, 2004, pp.302-313 [12] Tektronix technology, “Understanding and Characterizing Timing Jitter” [13] Agilent technology, “Jitter Analysis Techniques for High Data Rates” [14] M. Shimanouchi, “Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in Production,” ITC Proceedings, 2003, pp.48-57 [15] M. Maymandi-Nejad, M. Sachdev, “A Digitally Programmable Delay Element: Design and Analysis,” IEEE Transactions on VLSI Systems, 2003, pp.871-878 [16] N. R. Mahapatra, S.V. Garimella, A. Tareen, “An Empirical and Analytical Comparison of Delay Elements and A New Delay Element Design,” IEEE Computer Society Workshop on VLSI, 2000, pp. 81-87 [17] B. Razavi, “Design of Analog CMOS Integrated Circuit,” Wiley-IEEE Press, 2001 [18] B. Razavi, “Monolithic Phase-locked Loops and Clock Recovery Circuit,” Wiley-IEEE Press, 1996. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33439 | - |
dc.description.abstract | 在現今的高速通訊元件中,抖動已然成為資料可達到傳送品質的重要因素之一,隨著資料傳送頻寬的需求漸增,抖動的規格對高速傳送系統及匯流排來說是相當重要的。一般而言,元件抖動的規格是由自動測試設備(ATE)所測得,但是資料頻率快速的提升使得自動測試設備難以趕上期效能的要求。再者,近來大多數研究投注在抖動量測的部分。在本論文中,我們提出了一個低成本且可實現在晶片上的週期性抖動注入技術,為了達到系統層之內建式自我測試應用,並利用模擬去驗證我們的方法。 | zh_TW |
dc.description.abstract | For modern high speed communication devices, jitter has been an important factor of the achievable data transmission quality. With the growing demand on data bandwidth, meeting the jitter specification is crucial for high speed I/O and bus standards. Typically, jitter specifications are tested by external Automatic Test Equipment (ATE), but the growing data rate makes it difficult, if possible at all, for the ATE to catch up with the performance requirement. Most of the recent works concentrate on jitter measurement. In this thesis, a low-cost on-chip sinusoidal jitter injection technique for system level Built-In Self-Test (BIST) applications is proposed. Simulation results are demonstrated to validate the proposed technique. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T04:40:35Z (GMT). No. of bitstreams: 1 ntu-95-R93943093-1.pdf: 1176547 bytes, checksum: e5ad30cf5bbda5b50030310a38e0410c (MD5) Previous issue date: 2006 | en |
dc.description.tableofcontents | 致謝 ………………………………………………………………………………… i
中文摘要 …………………………………………………………………………… ii ABSTRACT …………………………………………………………….iii TABLE OF CONTENTS ………………………………………………iv LIST OF TABLE ………………………………………………………. v LIST OF FIGURE ……………………………………………………..vi CHAPTER 1 INTRODUCTION …………………………………… 1 1-1 Motivation and Background ………………………………………………. 1 1-2 Typical Architecture of the SerDes ………………………………………. 2 CHAPTER 2 PRELIMINARY WORKS FOR JITTER TOLERANCE TESTING ……………………………. 4 2-1 Jitter Definition ……………………………………………………………. 4 2-2 Jitter Categorization and Generation ……………………………………….6 2-3 Jitter Suppression ………………………………………………………….. 11 2-4 The Concept and Jitter Tracking Ability of Clock and Data Recovery …… 12 2-5 Jitter Tolerance Mask as the Specification ………………………………… 15 CHAPTER 3 JITTER INJECTION TECHNIQUES …………….. 17 3-1 Introduction ……………………………………………………………… 17 3-2 DDJ Injection with Passive Filters ………………………………………. 18 3-3 DDJ and PJ Injection with Enhance Loop-Back ………………………… 19 3-4 PJ Injection with Current Starved Delay Circuit ………………………… 21 3-5 Programmable Jitter Injection …………………………………………… 23 CHAPTER 4 THE PROPOSED JITTER INJECTION METHOD ……………………………………………………..25 4-1 Reference Work of theProposed Technique ………………………………25 4-2 The Proposed Jitter Technique …………………………………………... 27 CHAPTER 5 EXPERIMENTAL RESULT ……………………….. 36 5-1 Experimental Result of Analog-Controlled Delay Element …………..… 36 5-2 Experimental Result of Proposed Technique ……………………………. 38 CHAPTER 6 CONCLUSION ………………………………………. 43 REFERENCE ………………………………………………………….. 44 | |
dc.language.iso | en | |
dc.title | 以波管線為基礎的抖動產生技術應用於高速收發器之內建自我測試 | zh_TW |
dc.title | A Wave Pipeline-Based Jitter Generation Technique for High-Speed Transceiver Design-for-Test Applications | en |
dc.type | Thesis | |
dc.date.schoolyear | 94-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃弘一(Hong-Yi Huang),呂良鴻(Liang-Hung Lu) | |
dc.subject.keyword | 抖動,抖動產生技術, | zh_TW |
dc.subject.keyword | jitter,design-for-test, | en |
dc.relation.page | 45 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2006-07-19 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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