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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/32924Full metadata record
| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 李致毅(Jri Lee) | |
| dc.contributor.author | Sheng-Hann Wu | en |
| dc.contributor.author | 吳昇翰 | zh_TW |
| dc.date.accessioned | 2021-06-13T04:19:13Z | - |
| dc.date.available | 2007-07-31 | |
| dc.date.copyright | 2006-07-31 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-24 | |
| dc.identifier.citation | [1] Jaeha Kim et al.,“Circuit Techniques for a 40Gb/s Transmitter in 0.13_mCMOS,” ISSCC Dig. of Tech. Papers, pp. 150-151, Feb. 2005.
[2] M. Soyuer and R. G. Meyer, “Frequency limitations of a conventional phase-frequency detector,” IEEE J. Solid-State Circuits, vol. 25, pp. 1019–1022, Aug. 1990. [3] R. C. H. van de Beek, C. S. Vaucher, D. M. W. Leenaerts, N. Pavlovic, E. A. M. Klumperink, and B. Nauta, “A 2.5 to 10 GHz clock multiplier unit with 0.22 ps RMS jitter in a 0.18 _m CMOS technology,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 178–179. [4] B. Razavi, Design of integrated Circuits for Optical Communications, MaGraw-Hill, 2003. [5] Behzad Razavi, “Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits, A Tutorial” [6] Hai Tao et al, “40 43-Gb/s OC-768 16:1 MUX/CMU Chipset with SFI-5 Compliance,” IEEE J. Solid-State Circuits, vol. 38, pp. 2169-2180, Dec. 2003. [7] Mounir Meghelli et al., “A 0.18- m SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems,” IEEE J. Solid-State Circuits, vol. 38, pp. 2147-2154, Dec. 2003. [8] “An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL’s,” National Semiconductor Application Note 1001, July 2001. [9] A. Pottbacker et al., “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8Gb/s,” IEEE J. Solid-State Circuits, vol. 27, pp. 1747-1751, Dec. 1992. [10] Jri Lee et al., “A 20-Gb/s 2-t0-1 MUX and a 40-GHz VCO in 0.18-mm CMOS Technology,” Dig. of Symposium on VLSI Circuits, pp. 144-147, June 2006. [11] Jri Lee and Behzad Razavi, “A 40-GHz Frequency Divider in 0.18-mm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, April 2004. [12] Jri Lee and Behzad Razavi, “A 40-Gb/s Clock and Data Recovery Circuit in 0.18- | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/32924 | - |
| dc.description.abstract | 在這裡提出以0.18-um CMOS製程所製作20-GHz時脈倍頻單元, 應用於OC-768系統上, 採用雙迴路及三階濾波器以消除Jitter的影響. 所設計之電路達到輸出Jitter 0.2ps,rms及 4.5ps,pp同時在1.8V的偏壓下消耗40mW. | zh_TW |
| dc.description.abstract | A 20-GHz clock multiplication unit for SONET OC-768 systems employs dual loops and third-order loop filter to suppress the jitter. Realized in 0.18-um CMOS technology, this circuit achieves an output jitter of 0.2 ps,rms and 4.5 ps,pp while consuming 40 mW from a 1.8-V supply. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T04:19:13Z (GMT). No. of bitstreams: 1 ntu-95-R93943080-1.pdf: 3344675 bytes, checksum: 6804959a791862327e4b65cc2f456330 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | CHAPTER 1
Introduction 1.1 Next Generation .............................................................................................. p.01 1.2 Thesis Organization ........................................................................................ p.02 CHAPTER 2 General Consideration 2.1 Clock multiplication unit .................................................................................. p.05 2.1.1 Phase and Frequency Detector ................................................................. p.06 2.1.2 Charge pump and Loop Filter .................................................................. p.07 2.1.3 Voltage Controlled oscillator ................................................................... p.10 2.1.4 Frequency Divider ................................................................................... p.11 2.2 General Analysis Techniques for PLL ............................................................. p.13 2.1.1 Dynamics Mathematical Model .............................................................. p.13 2.1.2 Phase Noise ............................................................................................. p.15 CHAPTER 3 A 20-GHz Clock Multiplication Unit 3.1 Architecture and Building Blocks ................................................................... p.19 3.1.1 PD and V/I Converter ............................................................................. p.21 3.1.2 Frequency Detector ................................................................................. p.22 3.1.3 VCO/Divider/Buffer ............................................................................... p.23 3.2 Consideration ................................................................................................... p.24 3.2.1 Reference Feedthrough ........................................................................... p.24 3.2.2 Acquisition Range ................................................................................... p.11 3.4 Simulation Results ........................................................................................... p.33 3.3.1 Phase detector with V/I converter ........................................................... p.33 3.3.2 Voltage controlled oscillator .................................................................... p.33 3.3.3 Frequency divider .................................................................................... p.35 3.3.4 System analysis ........................................................................................ p.36 3.4 Experiment Results ........................................................................................... p.41 CHAPTER 4 Conclusions ................................................................................................ p.47 Bibliography ............................................................................................. p.49 | |
| dc.language.iso | en | |
| dc.subject | 鎖相迴路 | zh_TW |
| dc.subject | 時脈倍頻單元 | zh_TW |
| dc.subject | PLL | en |
| dc.subject | CMU | en |
| dc.subject | OC-768 | en |
| dc.title | 20-GHz時脈倍頻單元設計與分析以0.18-um CMOS製程製作 | zh_TW |
| dc.title | Design and Analysis of a 20-GHz Clock Multiplication
Unit in 0.18-um CMOS Technology | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien (Eric),盧信嘉(Hsin-Chia Lu) | |
| dc.subject.keyword | 鎖相迴路,時脈倍頻單元, | zh_TW |
| dc.subject.keyword | CMU,PLL,OC-768, | en |
| dc.relation.page | 52 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-07-24 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| Appears in Collections: | 電子工程學研究所 | |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| ntu-95-1.pdf Restricted Access | 3.27 MB | Adobe PDF |
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