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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/32872完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林茂昭 | |
| dc.contributor.author | Hong-Fu Chou | en |
| dc.contributor.author | 周泓甫 | zh_TW |
| dc.date.accessioned | 2021-06-13T04:17:46Z | - |
| dc.date.available | 2007-07-28 | |
| dc.date.copyright | 2006-07-28 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-24 | |
| dc.identifier.citation | [1] T. Richardson and R. Urbanke, “Efficient encoding of low density parity-check
codes,” IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 638–656, Feb. 2001. [2] T. Zhang and K. K. Parhi, “Joint (3, k)-regular LDPC code and decoder/encoder design,” to appear IEEE Transactions on Signal Processing, 2003. [3] Hao Zhong; Tong Zhang; Circuits and Systems, 2004. ISCAS '04. “Joint code-encoder-decoder design for LDPC coding system VLSI implementation”Proceedings of the 2004 International Symposium on Volume 2, 23-26 May 2004 Page(s):II - 389-92 Vol.2 [4] A flexible hardware encoder for low-density parity-check codes Lee, D.-U.; Luk, W.; Wang, C.; Jones, C.; Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on 20-23 April 2004 Page(s):101 - 111 [5] T. Zhang, Z. Wang, and K. K. Parhi, “On finite precision implementation of low-density parity-check codes decoder”, in Proc. of 2001 IEEE Int. Symp. on Circuits and Systems, Sydney, May 200 1. available at http://www.ece.umn.edu/groups/ddp/turbo/. [6] Tong Zhang and Keshab K. Parhi “VLSI Imnlementation-Oriented (3, k)-Regular Low-Density Parity-Check Codes”Department of Electrical and Computer Engineering University of Minnesota, Minneapolis, MN, USA E-mail:{ tzhang, parhi} @ece.umn.edu * [7] T. Zhang and K. K. Parhi, “A 54 MBPS (3, 6)-regular FPGA LDPC decoder,” IEEE Proc. of SIPS, pp. 127-132, 2002. [8] Fr´ed´eric GUILLOUD” Generic Architecture for LDPC Codes Decoding” T´el´ecom Paris - July 2004 [9] Sang-Min Kim and Keshab K. Parhi “Overlapped decoding for a class of quasi-cyclic LDPC codes [10] G. Hellstern, ”Coded modulation with feedback decoding trellis codes”, in Proc. IEEE Int. Conf. on Communications, Geneva, Switzerland, May 1993, pp. 1071-1075. [11]Hao Zhong,, and Tong Zhang,” Block-LDPC: A Practical LDPC Coding System Design Approach” IEEE Transactions on circuits and systems—I: regular papers,vol. 52, NO. 4, APRIL 2005 [12]Andrew J. Blanksby and Chris J. Howland , ” A 690-mW 1-Gb/s 1024-b, Rate-1/2 Low-Density Parity-Check Code Decoder ” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 3, MARCH 2002 [13] T. Zhang and K. K. Parhi, “A 54 MBPS (3, 6)-regular FPGA LDPC decoder,”in Proc. IEEE Int. Symp. Information Theory, Oct. 16–18, 2002,pp. 127–132. [14] Stephan ten Brink, Joachim Speidel, and Ran-Hong Yan, ”Iterative demapping and decoding for multilevel modulation”, Global Telecommunications Conference, 1998. GLOBECOM 98. The Bridge to Global Integration. IEEE Volume 1, 8-12 Nov. 1998 Page(s):579 - 584 vol.1 [15] Yeong-Luh Ueng, Chia-Jung Yeh, and Mao-Chao Lin, ”On trellis codes with a delay processor and a signal mapper”, IEEE Trans. on Comm. wol. 50, No. 12, pp.1906-1917, Dec. 2002. [16]MacKay’s Encyclopedia of Sparse Graph Codes, http://www.inference.phy.cam.ac.uk/mackay/codes/data.html [17] Hsuan-Yu Liu, Chien-Ching Lin, Yu-Wei Lin, Ching-Che Chung, Kai-Li Lin, Wei-Che Chang, Lin-Hung Chen, Hsie-Chia Chang, Chen-Yi Lee “A 480Mb/s LDPC-COFDM-Based UWB Baseband Transceiver”, ISSCC 2005 PROCESSING [18] G. Ungerboeck, ”Channel coding with multilevel/phase signals”, IEEE Trans. Inform.Theory, vol. IT-28, pp. 55-66, Jan. 1982. [19] R. Gallager, ”Low-density parity-check codes”, Cambridge, MA: MIT Press, 1963. [20] R. M. Tanner, ”A recursive approach to low complexity codes”, IEEE Tans. InformationTheory, pp. 533-547, Sept. 1981. [21] MacKay, D.J.C, S.T. Wilson, and M.C. Davey. October 1999. “Comparison of Constructionsof Irregular Gallager Codes.” Transaction on Communications 47:1449–1454. [22] http://grouper.ieee.org/groups/802/15/pub/TG3c.html [23] A. Batra et al., “Multi-band OFDM physical layer proposal for IEEE 802.15 task group 3a,” submitted to IEEE P802.15working group forWPANs, Sept. 2004. [24] ILiuqing Yang , Georgios B. Giannakis”Ultra wide-band Communication” IEEE SIGNAL PROCESSING MAGAZINE 26 26 N4 NOVEMBER 2004 [25] Chia-Jung Yeh, Yeong-Luh Ueng, Mao-Chao Linz, and Ming-Che Lu “ A Binary Turbo Coding with Interblock Memory” | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/32872 | - |
| dc.description.abstract | 根據參考文獻可知在編碼系統加上區塊記憶系統對於短編碼長度其錯誤更正能力具有大幅度改善,錯誤率效能都超越沒有區塊記憶系統。然而所需付出的代價是解碼複雜度以及速度增加。在此篇論文中，將實現LDPC 編碼解碼器以及具有延遲處理之LDPC 編解碼器，然後比較增加延遲處理器前後之硬體效能與錯誤更正能力差異。
在編碼器方面，我們根據Richardson 的高效率低複雜度之編碼器概念，然後Parhi 將此概念以位移循環方式之設計來建構編碼器。在這篇論文中，將此編碼器實現並且與以生成矩陣方式之編碼器比較效能與複雜度。在解碼器方面，我們是根據Parhi 所提出，使用Tanner graph 的概念以及部分平行式架構。 此外我們對區塊記憶解碼器之兩種設計， 即無遞迴式以及遞迴式之延遲處理解碼器架構都給予實現。在此篇論文中，描述此兩種硬體架構效能之優劣。 | zh_TW |
| dc.description.abstract | It has been shown that by properly introducing interblock memory to binary LDPC code, the decoded error rates can be significantly reduced for short code length.
However, the price is the increased decoding delay and decoding complexity. In this thesis, we conduct both the circuit design of LDPC codec and LDPC with interblock memory codec. Then, we compare the performance of both coding scheme based on complexity and the error rate. For the LDPC encoder, we consider two kinds of approaches. One was proposed by Richarson and was implemented by Parhi and the other is the generation matrix implemented by look up table. The decoder approach is implemented with partial parallel architecture. For the decoder of the LDPC code with interblock memory, it has been shown that there are two possible designs. One is the feedforward-only decoding and the other is the decoding with the feedback feature. In this thesis, we also compare the advantage and disadvantage of both designs based on the view of circuit application. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T04:17:46Z (GMT). No. of bitstreams: 1 ntu-95-R93942110-1.pdf: 4316050 bytes, checksum: 91faef517471d72fac509db9a1cd39d2 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | Contents
1 Introduction 6 2 Low-Density Parity Check codes 8 2.1 LDPC codes …………………………………………………8 2.2 Traditional decoding algorithm…………………………10 2.2.1 Message Passing Algorithm……………………………10 2.3 Some encoding methods……………………………………13 2.3.1 Lower-triangular shape based encoding………………13 2.3.2 I t e r a t i v e e n c o d i ng.…………………16 2.3.3 Low density generation matrices…………………16 2.3.4 Cyclic parity–check matrices……………………16 2.4 A study of Scheduling for LDPC decoder………………18 2.5 Survey of some current decoder architecture…………22 3 Circuit Design of LDPC Codec 24 3.1 The application on Communication Systems with LDPC Codes Receiver Side……………………………………………………………24 3.2 Basic concept of LDPC Implementation-oriented encoder/decoder design ……………………………………………………………28 3.3 LDPC decoder……………………………………………………30 3.4 LDPC encoder……………………………………………………38 3.5 Simulation and synthesis report………………………42 4 LDPC Code Design with Inter-block Memories 53 4.1 Two Delay processor scheme…………………………………53 4.1.1 Scheme A………………………………………………………55 4.1.2 Scheme B………………………………………………………58 4.2 Simulation……………………..……………… ………………………61 4.3 Hardware construction………….……………………………………..64 4.3.1 Encoder…………………………………………………………64 4.3.2 Decoder with interblock memory scheme A……………………66 4.3.3 Decoder with interblock memory scheme B……………………70 5 Conclusion 76 Bibliography 77 | |
| dc.language.iso | en | |
| dc.subject | 低密度同位元檢查碼 | zh_TW |
| dc.subject | 區塊記憶 | zh_TW |
| dc.subject | 電路設計 | zh_TW |
| dc.subject | LDPC | en |
| dc.subject | Implementation | en |
| dc.subject | circuit design | en |
| dc.subject | Interblock memory | en |
| dc.title | 使用區碼記憶之低密度同位元檢查碼編解碼器電路設計 | zh_TW |
| dc.title | Circuit Design for the LDPC Codec Using Interblock Memory | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 闕志達,蘇賜麟,韓永祥,楊谷章 | |
| dc.subject.keyword | 區塊記憶,低密度同位元檢查碼,電路設計, | zh_TW |
| dc.subject.keyword | Interblock memory,LDPC,circuit design,Implementation, | en |
| dc.relation.page | 79 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-07-25 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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