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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 張帆人 | |
dc.contributor.author | Yu-Cheng Chen | en |
dc.contributor.author | 陳佑政 | zh_TW |
dc.date.accessioned | 2021-06-13T04:13:34Z | - |
dc.date.available | 2011-07-28 | |
dc.date.copyright | 2006-07-28 | |
dc.date.issued | 2006 | |
dc.date.submitted | 2006-07-25 | |
dc.identifier.citation | [1] R. E. Best, Phase-locked loop: Design. Simulation, and Applications, McGraw-Hill International, 1997.
[2] E. D. Kaplan, Understanding GPS: principles and application. Artech House, London, 1996. [3] W. L. Mao, H. W. Tsao, and F. R. Chang,“Intelligent GPS receiver for robust carrier phase tracking in kinematic environments,” IEE Proceedings Radar, Sonar and Navigation, vol. 151, No. 3, pp.171-180, Jun. 2004. [4] O. Yaniv and D. Raphaeli, “Near-optimal PLL design for decision feedback carrier and timing recovery,” IEEE Trans. on Communication, Vol. 49, pp. 1669 - 1678, Sept. 2001. [5] F. M. Gardner, Phaselock Techniques. John Wiley, New York, NY, third ed., 2005. [6] J. C. Doyle, B.A. Francis, and A.R. Tannenbaum, Feedback Control Theory, Macmillan Publishing Company, Inc. 1992. [7] S. Boyd, L. El Ghaoui, E. Feron, and V. Balakrishnan, Linear Matrix Inequalities in System and Control Theory, SIAM, Philadelphia, 1994 [8] C. Scherer, P. Gahinet, and M. Chilali, “Multiobjective output feedback control via LMI optimization,” IEEE Trans. Autom. Control, vol. 42, pp. 896-911, 1997 [9] M. Chilali and P. Gahinet, “H∞ design with pole placement constraints: an LMI approach,” IEEE Trans. Autom. Control, vol. 41, pp. 358-367, 1996. [10] C. E. de Souza and U. Shaked, “An LMI method for output-feedback control design for system with parameter uncertainty,” Proceedings of the 37th IEEE Conference on decision and control, Tampa, Florida USA, pp.1777-1779, 1998. [11] N. S. Nise, Control Systems Engineering. John Wiley & Sons, Inc., 4th edition, 2004. [12] M. S. Braasch and A. J. Van Dierendonck, “GPS receiver architectures and measurements,” Proceedings of the IEEE, vol. 87, pp. 48–64, 1999. [13] S. Kanev, C.W. Scherer, M. Verhaegen, and B. De Schutter, “A BMI optimization approach to robust output-feedback control,” Proceedings of the 42nd IEEE Conference on decision and control, Maui, Hawaii USA, pp. 851-856, 2003. [14] 褚永誠,權重靈敏度函數最小化問題之降階控制器設計, 碩士論文,淡江大學電機工程學系,2006。 [15] G. F. Franklin, J. D. Powell and E. N. Abbas, Feedback Control of Dynamic System, Prentice Hall, 4th edition, 2002. [16] 繆紹綱、黃嘉淵:通訊系統模擬SystemView By ELANIX使用入門,全華科技圖書,1989。 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/32690 | - |
dc.description.abstract | 本論文提出了一個新型的迴路濾波器設計。在考慮/不考慮時間延遲因素之下,應用多目標的控制技術來設計濾波器,以同時達成多種目標。設計目標包含了降低雜訊頻寬、好的暫態響應(小的安定時間、小的最大超越量)以及大的增益邊限與相位邊限。
在濾波器的設計中,利用近年來發展的凸最佳化技巧(亦即線性矩陣不等式)將設計參數作適當的調整,以協調各項互相衝突的性能指標。我們的方法另有一項特色是可預先設定若干迴路濾波器的極點與零點,因此可以設計別具意義的PI形式迴路濾波器,其極點全部在原點。此外,我們提出的方法適用於任意階數的鎖相迴路濾波器設計。 在數值模擬的部分,本論文首先使用非線性的模型來模擬設計完成的迴路。在不考慮時間延遲因素的情形,將本論文所提出的PI形式濾波器設計,與一般的設計作比較。而在考慮時間延遲因素的情形,則比較本論文所提出的兩種濾波器設計的效果。最後,利用更逼真的模型來進一步驗證本論文所提出的設計之實用性。 | zh_TW |
dc.description.abstract | A new loop filter design method for phase locked loops (PLLs) is presented subject to loop with/without pure delay, which employs multi-objective control technique to deal with the various design objectives: small noise bandwidth, good transient response (small settling time, small overshoot), and large gain and phase margins.
Trade-off among the conflicting objectives is made via recently developed convex optimization skill (i.e., linear matrix inequality, LMI) in conjunction with appropriate adjustment of certain design parameters. One salient feature of the proposed method is that it allows one to specify some filter poles and zeros in advance, including the special case of PI form filter of which all the filter poles are at the origin. Moreover, the proposed method is applicable to PLL of any order. Numerical simulation on nonlinear PLL model is performed. For the case without considering delay, comparisons of our results with that by generic PI form loop filter design are made. As for the case taking time delay into account, comparisons between two proposed methods are made. Finally, more realistic model is employed to simulate the resulting PLLs for demonstration of the effectiveness of the proposed method in practice. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T04:13:34Z (GMT). No. of bitstreams: 1 ntu-95-R93921061-1.pdf: 1223809 bytes, checksum: e8fde4bcd64c600f14f802ccf8cafbcd (MD5) Previous issue date: 2006 | en |
dc.description.tableofcontents | 第一章 序論 1
1.1 研究動機 1 1.2 論文架構 2 第二章 預備知識 3 2.1 鎖相迴路(PLL) 3 2.1.1 工作原理 3 2.1.2 相位訊號 5 2.1.3 數學模型 6 2.1.4 頻率範圍的參數 11 2.2 數學基礎 13 2.2.1 系統與訊號的範數 13 2.2.2 LMI的定義 15 2.2.3 LMI分析式 16 第三章 不考慮時間延遲的迴路濾波器設計 19 3.1 設計目標 19 3.2 等價問題轉換 21 3.3 固定極點的迴路濾波器設計 27 3.4 PI形式迴路濾波器設計 30 第四章 考慮時間延遲的迴路濾波器設計 35 4.1 設計目標 35 4.2 等價問題轉換 37 4.3 一般形式迴路濾波器設計 42 4.4 PI形式迴路濾波器設計 44 第五章 設計結果與模擬分析 53 5.1 模擬軟體SystemView介紹 53 5.2 不考慮迴路延遲的設計與模擬結果 57 5.3 考慮迴路延遲的設計與模擬結果 65 5.4 更逼真的模擬結果 70 5.4.1 不考慮時間延遲 71 5.4.2 考慮時間延遲 74 第六章 結論與未來展望 77 6.1 結論 77 6.2 未來展望 77 參考文獻 79 | |
dc.language.iso | zh-TW | |
dc.title | 鎖相迴路之濾波器設計:LMI方法 | zh_TW |
dc.title | Filter Design for Phase-Locked Loop:An LMI Approach | en |
dc.type | Thesis | |
dc.date.schoolyear | 94-2 | |
dc.description.degree | 碩士 | |
dc.contributor.coadvisor | 周永山 | |
dc.contributor.oralexamcommittee | 王立昇,林君明,唐望 | |
dc.subject.keyword | 鎖相迴路,線性矩陣不等式, | zh_TW |
dc.subject.keyword | PLL,phase-locked loop,LMI, | en |
dc.relation.page | 80 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2006-07-25 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
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