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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 呂良鴻 | |
dc.contributor.author | Yu-Hsun Peng | en |
dc.contributor.author | 彭昱勛 | zh_TW |
dc.date.accessioned | 2021-06-13T03:51:47Z | - |
dc.date.available | 2006-07-28 | |
dc.date.copyright | 2006-07-28 | |
dc.date.issued | 2006 | |
dc.date.submitted | 2006-07-26 | |
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Kim, “A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13-um CMOS,” IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 899- 908, Apr. 2006. M. Tieout, C. Kienmayer, R. Thuringer, C. Sandner, H. D. Wohlmuth, M. Berry, and A. L. Scholtz, “17 GHz transceiver design in 0.13-um CMOS,” in Proc. 2005 IEEE RFIC Symposium, pp. 101-104, Jun. 2005. C. Lam, B. Razavi, “A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-um CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 35, no. 5, pp. 768-794, May. 2000. G. C. T. Leung, H. C. Luong, “A 1-V 5.2-GHz CMOS synthesizer for WLAN applications,” IEEE Journal of Solid-State Circuits, vol. 39, no. 11, pp. 1873-1882, Nov. 2004. [3] A. P. Wel, S. L. J. Gierkink, R. C. Frye, V. Boccuzzi, B. Nauta, “A Robust 43-GHz VCO in CMOS for OC-768 SONET applications,” IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp. 1159-1163, July. 2004. [4] S. Ko, J. –G. Kim, T. Song, E. Yoon, S. Hong, “K- and Q- bands CMOS frequency sources with X- band Quadrature VCO,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 9, pp. 2789-2800, Sep. 2004. [5] N. Pavlovic, J. Gosselin, K. Mistry and D. Leenaerts, “A 10GHz fre- quency synthesizer for 802.11a in 0.18-um CMOS,” in Proc. of the 30th European Solid-State Circuits Conference, pp. 367-370, Sep. 2004. [6] Y.-H. Peng and L.-H. Lu, “A Ku-band frequency synthesizer in 0.18-um CMOS technology,” to appear in IEEE Microwave and Wireless Components Letters. [7] J. Craninckz, M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divided-by-128/129 prescaler in 0.7-um CMOS,” IEEE Journal of Solid-State Circuits, vol. 31, no. 7, pp. 890-897, July. 1996. [8] N. Krishnapura, P. R. Kinget, “A 5.3-GHz programmable divider for HiPerLAN in 0.25-um CMOS,” IEEE Journal of Solid-State Circuits, vol. 35, no. 7, pp. 1019-1024, July. 2000. [9] X. –P. Yu, M. –A. Do, J. –G. Ma, K. –S. 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Talbi, J. Safran, A. Ray, and L. Wagner, “A power- optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate,” in Proc. Int. Symp. Low Power Electronics and Design, pp. 434-439, Aug. 2003. [1] J. –H. C. Zhan, J. S. Duster, K. T. Kornegay, “A 25-GHz Emitter Degenerated LC VCO,” IEEE Journal of Solid-State Circuits, vol. 39, no. 11, pp. 2062-2064, Nov. 2004. [2] L. Zhenbiao, K. O. Kenneth, “ A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator,” IEEE Journal of Solid-State Circuits, vol. 40, no. 6, pp. 1296-1302, Jun. 2005. [3] T. –H. Lin, W. J. Kaiser, “ A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop,” IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 424-430, Mar. 2004. [4] W. B. Wilson, U. –K. Moon, K. R. Lakshmikumar, L. Dai, “ A CMOS self-calibrating frequency synthesizer,” IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1437-1444, Oct. 2000. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/32478 | - |
dc.description.abstract | 近年來由於個人無線通訊系統的蓬勃發展以及無線通訊市場的快速成長,射頻前端接收發器的研究如雨後春筍般成長。其中以低功耗、低成本、高整合性電路為目前無線通訊科技的主流。CMOS 製程成為低價無線通訊系統的熱門製程。但是因為製程上先天的限制,對於高工作頻段(約10GHz以上)的頻率合成器設計仍是一個很值得去探討的課題。
在本論文中,將以實現Ku-band頻率合成器為主要研究專題。我們總共提出三各晶片,分別針對各種不同的電路限制來做改進並且提出相對應的解決方案。在第三章中,藉由提出一個改良式的Colpitts壓控振盪器,我們可以構成一個工作再Ku-band的頻率合成器。其工作頻率範圍從14.8GHz至16.9GHz,在輸出頻率為15GHz時,此頻率合成器的相位雜訊約為-104.5dBC/Hz@1-MHz offset。並且在2V的工作電壓下,電路總共消耗約70mW的功率。 為了克服電晶體先天上的速度瓶頸,在第四章中我們提出一個三模的相位切換式的前置除頻器,藉由此架構我們可以有效的增加前置除頻器的最高工作頻率,並且還可以同時達到較寬的鎖定範圍。並藉由一個15GHz的頻率合成器來驗證所提出的前置除頻器電路,其工作頻段從13.9GHz至15.6GHz,在14.4GHz的工作頻率下,其相位雜訊大小約為-103.8dBc/Hz@1-MHz offset。並且在1.8V的工作電壓下,電路總共約有70mW的功率消耗。 而最後我們提出一個工作在Ku-band的超寬頻的頻率合成器。同時使用切換電容和切換電感的技巧,我們得以實現一個工作頻率自12.5GHz至18.2GHz,並且擁有自動選頻機制的頻率合成器。 | zh_TW |
dc.description.abstract | The fast-growing market in personal wireless communications has motivated the development of fully integrated transceivers using a cost-efficient CMOS process. Frequency synthesizers are widely used to provide a stable, clean and programmable carrier frequency in modern communication systems. In order to satisfy the increasing demands and to avoid the over-crowded radio transmission, new wireless standards have been proposed at higher frequency bands. With the limitations on the cut-off frequency of the transistors, it is still a great design challenge to implement CMOS synthesizers operating at frequencies beyond 10 GHz.
In chapter 3 presents a fully integrated frequency synthesizer implemented in a 0.18-um foundry CMOS process. By employing a modified differential Colpitts VCO to improve the tuning range and the phase noise, the integer-N frequency synthesizer demonstrates an output frequency from 14.8 to 16.9 GHz, allowing wideband operations at Ku-band. Operated at an output frequency of 15 GHz, the proposed synthesizer exhibits a reference sideband power of -50 dBc and a phase noise of -104.5 dBc/Hz at 1-MHz offset. The fabricated circuit consumes a dc power of 70 mW from a 2-V supply voltage. A triple-modulus phase-switching prescaler for high-speed operations is presented in chapter 4. By reversing the switching order between the eight 45°-spaced signals generated by the 8:1 frequency divider, the maximum operating frequency of the prescaler is effectively enhanced. With the triple-modulus switching scheme, a wide frequency covering range is achieved. The proposed prescaler is implemented in a 0.18-um CMOS process, demonstrating a maximum operating frequency of 16 GHz without additional peaking inductors for a compact chip size. Based on the high-speed prescaler, a fully integrated integer-N frequency synthesizer is realized. The synthesizer operates at an output frequency from 13.9 to 15.6 GHz, making it very attractive for wideband applications in Ku-band. At an output frequency of 14.4 GHz, the measured sideband power and phase noise at 1-MHz offset are -60 dBc and -103.8-dBc/Hz, respectively. The fabricated circuit occupies a chip area of 1 mm2 and consumes a dc power of 70 mW from a 1.8-V supply voltage. A 12-18GHz frequency synthesizer with automatic frequency calibration is presented in chapter 5. By employing both of the switched-capacitor and switched-inductor methods, we can implement a wide-tuning range VCO. At the Ku-band, the proposed VCO achieve wideband operation which is about 36% of the tuning range. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T03:51:47Z (GMT). No. of bitstreams: 1 ntu-95-R93943004-1.pdf: 4698755 bytes, checksum: 8d1848c178c4cb1380daa5ff7c502211 (MD5) Previous issue date: 2006 | en |
dc.description.tableofcontents | Chapter1 Introduction 1
1.1 Motivation 1 1.2 Overview of the thesis 2 Chapter2 Synthesizer Background 3 2.1 General Considerations 3 2.1.1 Phase noise and reference spurs 3 2.1.2 Settling time 6 2.2 Basic Building Blocks of PLL 7 2.2.1 Phase and frequency detector 8 2.2.2 Charge pump 10 2.2.3 Voltage controlled oscillator 11 2.2.4 Frequency divider 11 2.2.5 Low pass filter 12 2.3 System Analysis 13 2.4 Noise Analysis 14 2.4.1 Phase noise at input 14 2.4.2 Phase noise of VCO 15 Chapter 3 A Ku-Band Frequency Synthesizer 17 3.1 Introduction 17 3.2 System Architecture 18 3.3 Circuit Implementation 19 3.3.1 Modified differential Colpitte voltage controlled oscillator 19 3.3.2 Frequency divider 22 3.3.3 PFD and charge pump 24 3.4 Experimental Results 25 3.5 Conclusion 29 3.6 References 30 Chapter 4 The 16-GHz Triple-Modulus Phase-Switching Prescaler 32 4.1 Introduction 32 4.2 The Triple-Modulus Phase-Switching Prescaler 34 4.2.1 Conventional phase-switching prescaler 34 4.2.2 The proposed phase-switching scheme 35 4.2.3 Design of a 16-GHz phase-switching prescaler 38 4.3 The 15-GHz Frequency Synthesizer 44 4.4 Experimental Results 48 4.4.1 The triple-modulus phase-switching prescaler 48 4.4.2 The 15-GHz frequency synthesizer 51 4.5 Conclusion 54 4.6 References 55 Chapter 5 12-18 GHz Fractional-N Frequency Synthesizer with Automatic Frequency Calibration 57 5.1 Introduction 57 5.2 The Wide Tuning Range VCO 58 5.2.1 The proposed VCO architecture 59 5.2.2 Switched-capacitor method 60 5.2.3 Switched-inductor methods 60 5.2.4 Proposed varactor scheme 62 5.3 The Automatic Frequency Calibration 63 5.3.1 Existing frequency calibration methods 63 5.3.2 The proposed automatic frequency calibration architecture 65 5.3.3 The circuit implementation of the AFC 66 5.4 12-18GHz Fractional-N Frequency Synthesizer 68 5.5 Simulation Results 70 5.6 Conclusion 73 5.7 References 74 Chapter 6 Conclusion 75 | |
dc.language.iso | en | |
dc.title | 互補式金氧半Ku頻帶頻率合成器之設計與實作 | zh_TW |
dc.title | Design and implementation of CMOS Ku-band frequency synthesizers | en |
dc.type | Thesis | |
dc.date.schoolyear | 94-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 鄧裕庭,闕河鳴,陳巍仁 | |
dc.subject.keyword | 頻率合成器,前置除頻器,Ku頻帶, | zh_TW |
dc.subject.keyword | syntheszier,prescaler,ku-band, | en |
dc.relation.page | 75 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2006-07-26 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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