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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳德玉(Dan Chen) | |
dc.contributor.author | Tien-chi Lin | en |
dc.contributor.author | 林天麒 | zh_TW |
dc.date.accessioned | 2021-06-13T03:23:30Z | - |
dc.date.available | 2007-07-31 | |
dc.date.copyright | 2006-07-31 | |
dc.date.issued | 2006 | |
dc.date.submitted | 2006-07-29 | |
dc.identifier.citation | 1. Oscar García, José A. Cobos, Roberto Prieto, Pedro Alou, and Javier Uceda “Single Phase Power Factor Correction: A Survey ” IEEE Transactions on Power Electronics, Vol. 18, No. 3, May 2003
2. IEC, Disturbances in supply systems caused by household appliances and similar electrical equipment, International Electrotechnical Commission Publication 1000, Parts 1-3, 1995 3. Dhaval Dalal, “Efficient Architectures for Internal and External Computer Power Supplies” On semiconductor 4. Shin, F. Y., D. Y. Chen, etc., “A procedure for Designing EMI Filters for AC Line Applications” IEEE Trans. On Power Electronics, pp. 170-181, Jan. 1996 5.Zheren Lai, Student Member, IEEE, and Keyue Ma Smedley, Senior Member, IEEE “A Family of Continuous-Conduction-Mode Power-Factor-Correction Controllers Based on the General Pulse-Width Modulator” IEEE Transactions On Power Electronics, Vol. 13, No. 3, May 1998 6. S. Wall and R. Jackson, “Fast controller design for practical power-factor correction systems,” in Proc. IEEE IECON, 1993, pp. 1027-1032 7. Chen Zhou, Raymond B. Ridley, and Fred C. Lee “Design And Analysis of Hysteretic Boost Power Factor Correction Circuit” Power Electronics Specialists Conference, 1990. PESC '90 Record., 21st Annual IEEE 11-14 June 1990 Page(s):800 – 807 8. Kwang-Hwa Liu and Yung-Lin Lin “Current Waveform Distortion in Power Factor Correction Circuit Employing Discontinuous-Mode Boost Converters” Power Electronics Specialists Conference, 1989. PESC '89 Record., 20th Annual IEEE 26-29 June 1989 Page(s):825 - 829 vol.2 9. Michael G. Negrete, “Design and Control of Photoflash Capacitor Charging Circuits” Master thesis, Massachusetts institute of technology, January 2004 10. Bill Andreycak ”Controlled On-time, Zero Current Switched Power Factor Correction” Unitrode Design Seminar - SEM800 Topic 3 ,1991 11. ”Compact Fixed Frequency Discontinuous or Critical Conduction Voltage Mode Power Factor Correction Controller” On Semiconductor NCP1601A,NCP1601B Data Sheet 12.徐建國 “使用頻率調變來抑制切換式電源供應器的EMI” 國立台灣大學電機工程研究所碩士學位論文, 2005 13. Jin-ho choi , Dong-young Huh, Young-seok Kim, “The Improved Burst Mode in the stand-by operation of Power Supply” Applied Power Electronics Conference and Exposition, 2004. APEC '04. Nineteenth Annual IEEE Volume 1, 2004 Page(s):426 - 432 Vol.1 14. Jindong Zhang, Jian wen Shao, Peng Xu and Fred C. Lee, “Evaluation of Input Current in the Critical Mode Boost PFC Converter for Distributed Power System” Applied Power Electronics Conference and Exposition, 2001. APEC 2001. Sixteenth Annual IEEE Volume 1, 4-8 March 2001 Page(s):130 - 136 vol.1 15. Takuya Ishii, Yoshio Mizutani , “Power Factor Correction Using Interleaving Technique for Critical Mode Converters” Power Electronics Specialists Conference, 1998. PESC 98 Record. 29th Annual IEEE Volume 1, 17-22 May 1998 Page(s):905 - 910 vol.1 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31890 | - |
dc.description.abstract | 在臨界模式CRM (critical mode) 中,當輸入弦波電壓波形在谷底的時候切換頻率會變高。在這段期間對輸入功因之改進本就沒太大影響,但切換損耗卻仍然高。因此本篇論文是針對在有限制最高頻率的情形下,將切換頻率高於一個上限時,停止在這段期間MOSFET作切換的動作,以減少開關損耗,提高輕載時的效率。並且在待機(standby) 的情況下希望能達到省能 (green mode) 的世界標準。因此使用此提倡之方法將在本論文中稱為削減型臨界模式 (truncated CRM) 。本論文中將以數學分析truncated CRM情形下的功因值、諧波成分、輸出功率、導通角度等等之間的關係。並將利用這樣的關係討論如何設計電感之大小以達到所要的功因值及諧波成份。
本論文也提到利用CRM之功因修正時可以以interleaving方式將兩組PFC合成以達到較大功率輸出。因此利用兩組各自輸出功率較小的PFC電路來並聯,來供應出一樣大小的功率可提升線路效率及降低電流漣波 (ripple) 。並利用推導的公式描繪出輸入與輸出電容電流漣波,以便了解兩組PFC做interleaving和單組PFC時電容之漣波(Ripple) 彼此間的差異。本論文將討論此漣波與電路其他之參數及工作情況之間的關係,這對設計時選擇電容將有助益。 | zh_TW |
dc.description.abstract | In a Critical-Mode Power Factor Correction circuit, the switching frequency is variable. The frequency can be considerably higher when the input voltage waveform is near the valley point. This leads to higher switching loss during this period of time. Since the contribution to power factor correction and output power throughput during this period is insignificant but MOSFET switching loses are high, it’s better just to cut off the MOSFET switch during this period. In other words, one can set a frequency limit beyond which MOSFET is cut off. This is called Truncated CRM operation in this thesis. This method saves power especially when the circuit is under stand-by mode. There is a mandate to reduce this type of loss because in many house-hold applications the equipment are most of the time at stand-by mode.
In the thesis, an analysis was conducted to find out how the various PFC performances such as power factor, harmonic current, and conduction angles depend on circuit parameter and working conditions. These relationships were also used to help design the Truncated-CRM PFC circuit in the thesis. Two CRM PFC circuits are often interleaved to provide higher output power. Because of interleaving, the ripple current of the capacitors can be reduced. An analysis was also conducted to find out the ripple information in terms of circuit parameters and operating conditions. This information is also useful to the designers. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T03:23:30Z (GMT). No. of bitstreams: 1 ntu-95-R93921021-1.pdf: 11717995 bytes, checksum: 2b869ff1e575b7d35437a44343b210c4 (MD5) Previous issue date: 2006 | en |
dc.description.tableofcontents | 口試委員會審定書 ............................................................................. i
誌謝 ....................................................................................................... ii 中文摘要 ............................................................................................. iii 英文摘要 ............................................................................................. iv 符號表 ................................................................................................. xv 第一章 緒論 ..................................................................................... 1 1.1 功率因數校正簡介................................................................. 1 1.2 以boost converter為主軸的功率因數校正電路 ........ 4 1.3 本論文焦點 ............................................................................. 6 第二章 功率因數校正電路各種動作原理及特性 ................. 9 2.1 連續模式功率因數校正 ...................................................... 9 2.1.1 動作原理 .......................................................................... 9 2.1.2 連續模式之優缺點 ........................................................ 13 2.2不連續模式功率因數校正 ................................................ 13 2.2.1動作原理 ......................................................................... 13 2.2.2 不連續模式功率因數校正特性 .................................... 15 2.3 功率因數校正電路損失的討論 ...................................... 18 2.3.1 MOSFET切換損失特性 ................................................ 18 2.3.2 二極體切換損失特性 .................................................... 24 2.3.3連續模式與不連續模式損耗的比較 ............................. 26 2.4 臨界模式功率因數校正 .................................................. 27 2.4.1 動作原理 ....................................................................... 27 2.4.2 臨界模式功率因數校正電路的特性 ........................... 30 2.4.3 切換損失的討論 ........................................................... 33 2.4.4 臨界模式的特性討論 ................................................... 35 2.5 分析臨界模式的優劣 ....................................................... 37 2.5.1 臨界模式與不連續模式的比較 ................................... 38 2.5.2 臨界模式與連續模式的比較 ....................................... 38 2.6 控制模式的選擇 ................................................................ 40 第三章 臨界模式在有限制切換頻率動作原理及特性 ..... 42 3.1 原理介紹 ............................................................................. 42 3.2 電路模擬介紹 .................................................................... 44 3.3 公式推導 ............................................................................. 49 3.4 電路設計條件方法 ........................................................... 51 3.5 輸入電流諧波成分計算結果與圖形 ........................... 57 3.6 輸出功率與切換頻率關係 ............................................. 65 3.7 輸出功率與導通時間的關係 ......................................... 67 3.8 輸出功率與功率因數的關係 ......................................... 69 3.9 導通角度的探討 ................................................................ 69 第四章 雙相功率因數校正在臨界模式時的動作原理及特性 .......................................................................................................... 72 4.1 兩相臨界模式功率因數校正電路特性 ....................... 72 4.2 輸入電容電流(Icin)漣波的特性 ..................................... 77 4.2.1 CASE A: Vin(t) = 0.5Vo ............................................... 78 4.2.2 CASE B: Vin(t) < 0.5Vo ............................................... 79 4.2.3 CASE C: Vin(t) > 0.5Vo ............................................... 80 4.3 輸出電容電流(Icout)漣波的特性 ................................... 82 4.3.1 CASE A:Vin(t) < 0.5Vo ................................................. 82 4.3.2 CASE B:Vin(t) = 0.5Vo ................................................. 84 4.3.3 CASE C:Vin(t) > 0.5Vo ................................................. 84 4.4 兩相臨界模式功率因數校正電路電流波形圖 ......... 87 4.4.1 求得電流波形運算方法解析 ....................................... 87 4.4.2 運算結果 ....................................................................... 90 第五章 結論與未來發展 .......................................................... 102 5.1 結論 .................................................................................... 102 5.2 未來發展 ........................................................................... 103 參考文獻 .......................................................................................... 104 | |
dc.language.iso | zh-TW | |
dc.title | 削減式臨界模式功率因數改善電路的特性分析 | zh_TW |
dc.title | Characteristics of Truncated Critical-Mode Power-Factor-Correction Circuit | en |
dc.type | Thesis | |
dc.date.schoolyear | 94-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 劉志文,許源裕,劉光華 | |
dc.subject.keyword | 功率因數改善,臨界模式, | zh_TW |
dc.subject.keyword | PFC,CRM,Critical-Mode,Power Factor Correction, | en |
dc.relation.page | 106 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2006-07-30 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
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