請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31396完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳德玉(Dan-Y Chen) | |
| dc.contributor.author | Cheng-Chung Yang | en |
| dc.contributor.author | 楊正中 | zh_TW |
| dc.date.accessioned | 2021-06-13T02:47:41Z | - |
| dc.date.available | 2009-08-01 | |
| dc.date.copyright | 2007-08-01 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-07-30 | |
| dc.identifier.citation | [1] Yuancheng Ren, Ming Xu, Julu Sun, and Fred C. Lee, “A family of high power density unregulated bus converters,” IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 5, SEPTEMBER 2005
[2] Hong Huang, “Coordination of design issues in the intermediate bus architecture, “APEC 2005, Volume 1, Issue , 6-10 March 2005 Page(s) 169 - 175 Vol. 1 [3] R. D. Middlebrook, “Input filter considerations in design and application of switching regulators,” IEEE Industry Applicat. Soc. Annu. Meeting, 1976 Record. [4] Robert W. Erickson, Dragan Maksimovic, Fundamentals of power electronics, second edition, SCI-TECH publishing Co., Ltd [5]Carl M. Wildrick, Fred C. Lee, Fellow, IEEE, Bo H. Cho, Member, IEEE, and Byungcho choi, Member, “A method of defining the load impedance specification for a stable distributed power system,” IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL.10, pp.280-285, May 1995. [6] Xiaogang Feng, Zhihong Ye, Kun Xing, Fred C. Lee, Dusan Borojevic, “Individual load impedance specification for a stable DC distributed power system,” in Proc. 1999 IEEE appl. Power Electron. Conf. (APEC’99), Dallas, TX, March 1999, pp. 923-929. [7] Seiya Abe, Masahiko Hirokawa, Toshiyuki Zaitsu and Tamotsu Ninomiya, “Study of stabilization design for On-Board distributed power architechture.” 12th International Power Electronics and Motion Control Conference,Aug. 2006, pp. 636-640 [8] “AP 200 Parallel Frequency Response Analyzer Application Note”, http://www.ridleyengineering.com/downloads/AP200Notes.pdf [9] Delphi Series Q48SB, 480W Bus Converter DC/DC Power Modules: 48V in, 12V/40A out, Delta Electronics, Inc. http://www.delta.com.tw/product/ps/dcdc/std/download/data_sheet/DS_Q48SB12040_02162006.pdf [10] Delphi DNL10, Non-Isolated Point of Load DC/DC Power Modules: 8.3-14Vin, 0.75-5.0V/16A out, Delta Electronics, Inc. http://www.delta.com.tw/product/ps/dcdc/std/download/data_sheet/DS_DNL10SMD16_05102007D.pdf [11] Measurement of Power Supply transfer function Part II, Delta electronic R&D labortary | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31396 | - |
| dc.description.abstract | 現行的直流對直流分散式電壓源系統(DC-DC Distributed Power System, DC-DC DPS)所廣泛使用的中轉排線架構(Intermediate Bus Architecture, IBA)由中轉母線轉換器(Bus Converter, BC)與多個負載點轉換器(point-of-loads, POLs)掛載其後所組成。IBA架構在整合上最大的問題在於當電壓源子系統(BC)與負載子系統(POLs)在整合後阻抗會彼此干擾並造成系統穩定度與效能的衰減，而在之前的研究發現，透過比較電壓源的輸出阻抗與負載的輸入阻抗則可避免影響系統穩定度與減輕系統間相互干擾的問題。所以在設計之初必需將個別系統的阻抗加以詳細分析。
本篇論文以商用的IBA架構掛載多個POLs與POLs不同的輸出做探討。利用POLs閉迴路輸入阻抗的特性區間，配合奈氏穩定度準則來建立電壓源子系統輸出阻抗在不同區間內與負載子系統輸入阻抗的交疊限制，以確保IBA系統在安全的穩定度範圍以內。電路的實測與數學小信號模擬亦獲得比較驗證。 | zh_TW |
| dc.description.abstract | An intermediate bus architecture (IBA), consisting of a bus converter (BC) and point of loads (POLs), has become very popular in dc-dc distributed power system applications. When a BC modules are connected with POLs, system interactions may cause system instability or performance degradation. It was previously reported that by comparing the output impedance of the source impedance and the input impedance of a single POL, one can avoid system instability and alleviate potential performance degradation. Therefore impedance of individual subsystems must be analyzed carefully before the system coordinated.
In this thesis, this theory was applied to a commercial IBA with multiple POLs. Impedance characteristics of POL section and BC modules were used with Nyquist theorem to define the limitation of impedances and ensure the IBA system stability margin. Test results and mathematical calculations were compared with good agreement. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T02:47:41Z (GMT). No. of bitstreams: 1 ntu-96-J94921051-1.pdf: 7126720 bytes, checksum: bfc94498e3efbbf740c1c38cf6a9bfab (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | 誌謝 ………………………………………………………………………… I
中文摘要 ………………………………………………………………………… II 英文摘要 ………………………………………………………………………… III 目錄 …………………………………………………………………………IV 圖目錄 …………………………………………………………………………VI 表目錄 …………………………………………………………………………VIII 第一章 緒論 …………………………………………………………………………1 1.1 簡介 …………………………………………………………………………1 1.2 研究動機 ……………………………………………………………………….2 1.3 論文架構………………………………………………………………………...3 第二章 阻抗特性與穩定度之影響…………………………………………………..4 2.1 簡介……………………………………………………………………………...4 2.1.1 轉換器負阻抗對穩定度之影響 ……………………………………… ...4 2.1.2 阻抗交疊對轉換器迴授控制之影響 ……………………………………6 2.2 輸入濾波器與轉換器穩定度…………………………………………………...7 2.2.1 轉換器小信號轉移函數…………………………………………………..7 2.2.2 輸入濾波器與轉換器阻抗對轉移函數的影響…………………………..9 2.3 系統穩定度的判斷…………………………………………………………….14 2.3.1 線電壓轉移函數修正項…………………………………………………14 2.4 輸入濾波器穩定度與分散式電壓源系統穩定度…………………………….17 第三章 分散式電壓源之系統穩定度………………………………………………18 3.1 簡介…………………………………………………………………………….18 3.2 輸入與輸出阻抗……………………………………………………………….18 3.2.1 電壓源子系統之輸入阻抗..……………………………………………..19 3.2.2 負載子系統的輸入阻抗……...………………………………………….21 3.2.3 單級與多級負載子系統的輸入阻抗………………..…………………..22 3.3 系統副迴圈與相對穩定度…………………………………………………….26 3.3.1 系統增益邊限G.M. …………………………………………………......27 3.3.2 系統相位邊限P.M. ………………………………………………….......28 3.3.3 阻抗的相對位置與穩定度…………………………………………........29 (a) 輸出阻抗峰值(|Zo,s|Max)在區 I…………………………………........30 (b) 輸出阻抗峰值(|Zo,s|Max)在區 II與區III………………………........31 (c) 不同負載子系統的總輸入阻抗………………………………….......35 第四章 阻抗的量測與模擬驗證……………………………………………………40 4.1 簡介………………………………………………………………………….....40 4.1.1 測量儀器與模擬程式………………………………………………........40 4.1.2 系統電路………………………………………………………………....41 4.2 電壓源子系統模組(Q48SB)輸出阻抗的模擬與實測 ………………………..42 4.2.1 MathCAD模擬電壓源子系統模組(Q48SB)輸出阻抗………………….42 4.2.2 Q48SB電路實測與比較………………………………………….…........44 4.3 負載子系統DNL 10輸入阻抗的模擬與實測…………………………..........47 4.3.1 MathCAD模擬與量測輸入阻抗 ……………………………………......48 4.3.2 分散式電壓源系統穩定度模擬……………………………………........52 4.4 實測結論……………………………………………………………………….53 第五章 結論與未來研究方向………………………………………………………54 附錄 I. 轉換器閉迴路輸入阻抗之推導……………………………………………56 附錄 II. POL之小信號數學模擬 …………………………………………………..58 附錄 III. IBA之系統穩定度模擬 …………………………………………………..63 附錄 IV. 實測與小信號模擬比較………………………………………………… 66 | |
| dc.language.iso | zh-TW | |
| dc.subject | 分散式電壓源系統 | zh_TW |
| dc.subject | 小信號穩定度 | zh_TW |
| dc.subject | 阻抗分析 | zh_TW |
| dc.subject | 中轉排線架構 | zh_TW |
| dc.subject | intermediate bus architecture | en |
| dc.subject | small-signal analysis | en |
| dc.subject | impedance criterion | en |
| dc.subject | Distributed power system | en |
| dc.title | 商用直流分散式電壓源系統之小信號穩定度分析 | zh_TW |
| dc.title | Small Signal Stability Analysis of a Commercial DC Distributed Power System | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 許源浴(Yuan-Yih Hsu),呂錦山(Ching-Shan Leu) | |
| dc.subject.keyword | 分散式電壓源系統,中轉排線架構,阻抗分析,小信號穩定度, | zh_TW |
| dc.subject.keyword | Distributed power system,intermediate bus architecture,impedance criterion,small-signal analysis, | en |
| dc.relation.page | 79 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2007-07-30 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-96-1.pdf 未授權公開取用 | 6.96 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。