適用良率評估應用之類比電路模型建立技術

Abstract

隨著IC製程進步，電晶體尺寸面積縮小，現今製程變異已是影響良率的重要因素之一。在製程變異的影響下，IC的效能將異於其理想狀況，導致部分產品雖然可以運作，但其效能已不符合規格。蒙地卡羅分析法是一個常用的良率分析方法，藉由了解製程變異的機率分布，大量模擬實際的電路參數組合，來預測電路設計的良率。藉由蒙地卡羅分析法，我們可以預測良率，但是這個分析法卻有著耗費大量電路模擬時間的缺點。 Macromodel技術可用來加速電路模擬，其概念是以較精簡的模型替換電路的內部區塊（例如放大器）來達到模擬速度加快的目的。然而此一技術無法直接應用在良率分析上。因為在蒙地卡羅分析法中，每一個產生的電路參數組合皆有著不同的電路效能，以致於必須耗費大量的時間來產生其替代模型。 在這篇論文中，我們改善了Macromodel技術，加快模型建立速度。對於需要大量電路參數組合的蒙地卡羅分析法，有著顯著的改善效果。在實驗結果分析方面，我們以一Flash ADC做為實驗電路，實驗結果為良率分析速度提升3.7倍，電路模擬速度提升4倍，電路效能是否符合規格的預測準確率在94.17 %左右。

As the IC fabrication technology advances, the transistor feature size keeps shrinking and it is possible now to integrate a complete system on a chip. However, as the device size decreases, the inevitable process variations become an important factor of manufacturing yield. Under the influence of process variations, the performances of the fabricated IC's deviate from those of the nominal design. As a result, some IC's may still function, but their specifications are out of the acceptable range. Monte Carlo simulation is a commonly used technique for yield estimation. Given the process variation distribution, a sufficient large number of circuit instances are generated to match the fabrication distribution. Then, all the generated instances are simulated. Then, one can predict the performance distribution and yield based on the simulation results. The problem with Monte Carlo simulation is the required long circuit simulation time. Macromodel is a commonly used technique to speed up circuit simulation. The idea is to replace a circuit block, e.g., OPAMP, with a reduced model. However, for yield estimation applications, the macro-modeling process has to be performed for each circuit block instance because they are different in the existence of process variations. In this thesis, we propose a macromodel technique which is specially useful for yield estimation applications where a large number of macromodels have to be generated for the same circuit block. We use a flash ADC to validate our technique, with the proposed macromodeling technique, the speed up of yield estimation is about 3.7 times, the speed up of circuit simulation is 4 times, and the pass/fail classification accuracy is about 94.17%.