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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Bo-Hua Chen | en |
| dc.contributor.author | 陳勃樺 | zh_TW |
| dc.date.accessioned | 2021-06-13T02:46:16Z | - |
| dc.date.available | 2006-10-25 | |
| dc.date.copyright | 2006-10-25 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-10-16 | |
| dc.identifier.citation | [Artisan 99] TSMC 0.18 μm Process 1.8-Volt SAGE-XTM Standard Library Databook.
[Brglez 89] Brglez F., D. Bryan, and K. Kozminski, “Combinational Profiles of Sequential Benchmark Circuits,” ISCAS, Vol.14,no2, pp.1929-1934, MAY 1989. [Butler 04] K. Butler, J. Saxena, and et. al., “Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques,” IEEE proceedings – International Test Conference, pp.355 – 364, 2004. [Chen 06] Bo-Hua Chen and J. C.-M. Li, “Complemented Response Cell (CRC) : A Low Peak Power Testing Technique,” VLSI/CAD Symposium, 2006. [Bushnell 00] Bushnell M.L. and V.D. Agrawal, Essentials of Electronic Testing, Kluwer Academic Publishers, Boston, 2000. [Chiu 05] Chiu, M.H.;Li, J. C.M., “Jump Scan: A DFT Technique for Low Power Testing” Proc. 23th VLSI Test Symposium, 2005. (VTS 2005), IEEE CS Press, Palm Spings, Calif., 2005, pp.277-282. [Gerstendorfer 99] S. Gerstendorfer, H.J. Wunderlich, “Minimized Power Consumption for Scan-Based BIST,” Proc. IEEE Int’l Test Conf., pp.77-84, 1999. [Girard 02] P. Girard, “Survey of Low-Power Testing of VLSI Circuits”, IEEE Design and Test of Computers, Vol.19, pp.82-92, May-June 2002. [Goel 81] Goel, P., “An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits,” IEEE Trans. On Computers, Vol.C-30, No.3, pp.215-222, Mar. 1981. [Hertwig 98] Hertwig, A. and H.J. Wunderlich, “Low Power Serial Built-in Self Test,” Proc. 3rd European Test Workshop, pp.49-53, 1998. [Joshi 05] Kirti Joshi, Eric MacDonald, “Reduction of Instantaneous Power by Ripple Scan Clocking,” Proc. IEEE 23th VLSI Test Symp., 2005 (VTS’05) [Lee 05] Chun-Yi Lee and James Chien-Mo Li, “Segment Weighted Random BIST(SWR-BIST): A Low Power BIST Technique,” IEEE Proceedings – Asian Solid State Circuits Conference (A-SSCC) 2005. [Li 04] Li, J. C.M, “A Design for Testability Technique for Low Power Delay Fault Testing,” IEICE Transactions on Electronics, v E87-C, n 4, April, 2004, pp.621-628 [McCluskey 00] E.J. McCluskey, Tseng, C.W., “Stuck-Fault vs. Actual Defects,” Proc. Int’l Test Conf., pp.3356-343, 2000. [Miller 01] M. Miller, “Next generation burn-in and test systems for Athlon microprocessors: hybrid burn-in,” in AMD Burn-In and Test SocketWorkshop, Session5, 2001. [Nicolici 04] Paul Rosinger,Bashir M. Al-Hashimi, and Nicola Nicolici, “Scan Architecture with Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction,” IEEE Trans. Computer-Aided Design, Vol.23, no.7, July.2004, pp.1142-1153. [Power Compiler 02] Power Compiler User Guide Manual, Syonpsys, Release 2002.05, May 2002, ch2. [Reddy 98] V. Dabholkar, S,Chakravarty, I. Pomeranz, and S. Reddy, “Techniques for Minimizing for Power Dissipation in Scan and Combinational Circuits during Test Application,” IEEE Trans. On Computer-Aided-Design, vol. 17, no.12, pp.1325-1333, 1998. [Sankaralingam 00] R.Sankaralingam, R. Oruganti, N. Touba, “Static Compaction Techniques to Control Scan Vector Power Dissipation,” Proc. VLSI Test Symp., pp.35-40, 2000. [Sankaralingam 01] R.Sankaralingam, B. Pouya and N. A. Touba, “Reducing Power Dissipation During Test Using Scan Chain Disable,” Proc. IEEE 19th VLSI Test Symp., pp.319-324, 2001. [Sinanoglu 02] P. Sinanoglu, I. Bayraktaroglu, and A. Orailoglu, “Test Power Reduction through Minimization of scan Chain Transitions,” Proc. IEEE 20th VLSI Test Symp., 2002. [Touba 02(a)] Ranganathan Sankaralingam, Nur A. Touba, “Inserting Test Points to Control Peak Power During Scan Testing,” Proc. IEEE 17th International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’02), 2002. [Touba 02(b)] Ranganathan Sankaralingam, Nur A. Touba, “Controlling Peak Power During Scan Testing,” Proc. IEEE 20th VLSI Test Symp., 2002. [Wen 05] Xiaoqing Wen , Yoshiyuki Yamashita , Seiji Kajihara , Laung-Terng Wang , Kewal K. Saluja , and Kozo Kinoshita, “On Low-Capture-Power Test Generation for Scan Testing,” Proc. IEEE 23th VLSI Test Symp., 2005. [Wen 06] Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K.Saluja , Laung-Terng Wang, Khader-Hafez, and Kozo Kinoshita, “A New ATPG Method for Efficient Capture Power Reduction During Scan Testing,” Proc. IEEE 24th VLSI Test Symp., 2006 , pp.58-63. [Whetsel 00] L. Whetsel, “Adapting scan architectures for low power operation” IEEE International Test Conference (TC), 2000, pp.863-872. [Yoshida 03] T.Yoshida and W. Watari, “A New Approach for Low Power Scan Testing,” Proce. Intl. Test Conf., pp.480-487, 2003. [Ziemer] Ziemer R.E. and Peterson R.L., “Introduction to Digital Communication,” 2nd edt. Prentice Hall, 2001. [Zorian 93] Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Design,” Proc. 11th IEEE VLSI Test Symp., pp.4-9, 1993. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31374 | - |
| dc.description.abstract | 本論文提出一個低峰值功率可測試技術，其名稱為互補式輸出資料單元，主要是可降低在系統時脈時的峰值功率。此技術控制掃瞄鍊上特定的幾個掃瞄單元，使他們在系統時脈前後保持不變。在此技術中還提出一個計分的方法，其目地是用來選擇掃瞄鍊上特定的掃瞄單元並且將他們用互補式輸出資料單元置換。此技術跟已發展的低功率可測試設計最大的不同點在於此技術只要更動原來設計非常少的部分就可以達到不錯的效果。在ISCAS'89基準電路的實驗顯示，此技術可以將S38417的峰值功率降低57%。 此技術的特色在於即不需要額外的控制訊號也不需要增加額外的繞線，此外，此技術不會降低錯誤覆蓋率而且增加的面積相對很小。 | zh_TW |
| dc.description.abstract | This thesis presents a novel low peak power DFT technique, called Complemented Response Cell (CRC), to reduce the peak power at the system clock. This technique controls the data input of specified scan cells such that their contents remain unchanged before and after the system clock. A scoring method is proposed to select only a small number of scan cells replaced by CRC. The proposed technique is very different from the pervious technique is that it requires minimum change in the existing MUX-scan design for testability (DFT) methodology. According to the experimental data on ISCAS’89 benchmark circuits, the CRC technique reduces the peak power by up to 57% (S38417). In the CRC technique, neither extra control signal nor extra routing of scan chain is needed. Besides, there is no fault coverage loss and the area penalty is very small. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T02:46:16Z (GMT). No. of bitstreams: 1 ntu-95-R93943104-1.pdf: 1189324 bytes, checksum: c12242e4416f793228eec6be9bf50053 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | 摘要 I
Abstract II Table of Contents III List of Figures V List of Tables VI Chapter 1. Introduction 1 1.1 Motivation 1 1.2 Low Peak Power Techniques 3 1.3 Contributions 4 1.4 Thesis Organization 5 Chapter 2. Background 6 2.1 Power Dissipation 6 2.2 Past Research In Low Average Power 9 2.2.1 [Sinanoglu 02] 9 2.2.2 [Hertwig 89][Gerstendorfer 99] 10 2.2.3 [Li 04] 11 2.2.4 [Touba 02(a)] 12 2.3 Past Research In Low Peak Power 14 2.3.1 Shift Power Reduction 14 2.3.2 Capture Power Reduction 17 2.3.3 Hardware Design for Low Power DFT 21 Chapter 3. The Proposed Technique 24 3.1 Circuit Model 24 3.2 Complemented Response Cell 26 3.3 Design Flow of Implementation 30 3.3.1 CRC Selection 30 3.3.2 CRC Selection Procedure 33 3.3.3 Peak Power Threshold 34 3.3.4 Tracing Fanout Cone 37 Chapter 4. Experimental Results 39 4.1 ISCAS’89 Benchmark Circuit Simulation 39 4.2 Low Power Communication Chip 42 4.2.1 System Specification 42 4.2.2 Function of Low Power Receiver 44 4.2.3 Back-end flow with CRC procedure 45 4.2.4 Implementation Results 49 4.2.5 Measurement Results 51 4.2.6 Power Measurement 54 Chapter 5. Discussion and Future work 58 5.1 Silicon Debug 58 5.2 Further Improvements and Modifications of CRC 59 5.2.1 CRC with Toggle Suppression Technique 59 5.2.2 CRC with Low Power ATPG 60 5.3 CRC BIST 61 5.3.1 Structure of CRC BIST 61 5.3.2 Simulation Results 64 5.4 Useful rules for the CRC procedure 65 Chapter 6. Summary 69 Appendix I [Chen 06] 70 Appendix II Simulation of Test Bench 74 References 78 | |
| dc.language.iso | en | |
| dc.subject | 測試 | zh_TW |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 測試技術 | zh_TW |
| dc.subject | 低峰值功率 | zh_TW |
| dc.subject | testing | en |
| dc.subject | design-for-tes | en |
| dc.subject | low power | en |
| dc.subject | low peak power | en |
| dc.title | CRC:低峰值功率可測試技術設計 | zh_TW |
| dc.title | Complemented Response Cell (CRC) : A Low Peak Power design for Testability Technique | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃俊郎(Jiun-Lang Huang),饒建奇(Jiann-Chyi Rau) | |
| dc.subject.keyword | 測試技術,低功率,低峰值功率,測試, | zh_TW |
| dc.subject.keyword | design-for-tes,low power,low peak power,testing, | en |
| dc.relation.page | 81 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-10-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-95-1.pdf 未授權公開取用 | 1.16 MB | Adobe PDF |
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