使用延遲鍊頻率偵測器之3.125Gb/s時脈資料回復電路之設計與實現

Abstract

時脈資料回復電路在有線通訊系統中扮演一個重要的角色，將經過長距離傳輸後具有雜訊和抖動的資料回復成乾淨的資料以利下一級電路的使用。而電路的實現通常是使用鎖相迴路的方式達成目的，在實現架構上也有多種的選擇。本論文將分為兩個主要部份來介紹，在進入主題之前，會介紹一些時脈資料回復電路在不同架構上的實現方式。 在第一部份的3.125Gb/s半速率時脈資料回復電路中，利用一個源極追隨器增加環振盪器的線性可調範圍，使用DQFD可避免在頻率鎖定後仍然產生輸出影響充電泵造成頻率漂移。量測的結果，在1.8伏特電源供應下消耗108.4毫瓦，輸入231-1的PRBS得到時脈的峰對峰抖動和方均根抖動分別為55.6微微秒和6.61微微秒。 在本論文的第二部份，把時脈資料回復電路換成1/4速率的架構，提供兩個相差2個位元時間的時脈讓延遲鍊頻率偵測器對振盪器頻帶做選擇，選頻完成後數位電路會關掉偵測器主體以達省電功能。量測的結果，在1.8伏特電源供應下消耗103.74毫瓦，輸入2.48832Gb/s 27-1的PRBS得到時脈的峰對峰抖動和方均根抖動分別為31.1微微秒和5.06微微秒。

A clock and data recovery circuit plays an important role in wireline communication systems. It serves to recover the data with jitters and noises passed through long-distance transmission. The implementation is usually achieved by a phase-locked loop (PLL), and there are many choices for the implementation architectures. This work is divided into two parts: a half-rate CDR and a quarter-rate CDR with the delay-chain frequency detector will be reported. A 3.125Gb/s half-rate clock and data recovery circuit is implemented first. A source follower is utilized to increase the linear tuning range of the ring oscillator. Half-rate digital quadricorrelator frequency detector (DQFD) is used to avoid the frequency drift due to the active charge pump when loop is locked. The measured power consumption is 108.4mW under a 1.8V supply voltage. The measured clock peak-peak jitter and rms jitter under 231-1 PRBS are 55.6ps and 6.61ps, respectively. In the second part, the CDR is changed into the 1/4-rate architecture. Two clocks with two bit times difference are applied to the delay-chain frequency detector to choose the operating band of the VCO. After completing the operation of frequency selection, digital control circuits will turn off the core of the frequency detector. The measured power consumption is 103.7mW under a 1.8-V supply voltage. The measured clock peak-peak jitter and rms jitter with 2.4883Gb/s 27-1 PRBS are 31.1ps and 5.06ps, respectively.