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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/30663完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂良鴻 | |
| dc.contributor.author | Chien-Wei Yu | en |
| dc.contributor.author | 游建威 | zh_TW |
| dc.date.accessioned | 2021-06-13T02:11:38Z | - |
| dc.date.available | 2014-08-03 | |
| dc.date.copyright | 2011-08-03 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-08-01 | |
| dc.identifier.citation | [1]B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2003
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[19]G.-Y. Wei et al., “A 500-MHz MP/DLL clock generator for a 5-Gb/s backplane transceiver in 0.25-_m CMOS,” presented at the IEEE Solid-State Circuits Conf., Feb. 2003. [20]M. Combes, K. Dioury, and A. Greiner, “A portable clock multiplier generator using digital CMOS standard cells,” IEEE J. Solid-State Circuits, vol. 31, pp. 958–965, July 1996. [21]G. Chien and P. Gray, “A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS application,” IEEE Int. Solid- State Circuits Conf. Dig. Tech. Papers, Feb. 2000 pp. 202-203, 458. [22]S. Tam et al., “Clock generation and distribution for the first IA-64 microprocessor,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 1545–1552, Nov. 2000. [23]Savoj, J, Razavi, B, “A 10-Gb/s CMOS clock and data recovery circuit,” in Symp. VLSI Circuit Dig. Tech .Paper, pp. 136 – 139 , Jun 2000. [24]Young-Suk Seo, Jang-Woo Lee, Hong-Jung Kim, Changsik Yoo, Jae-Jin Lee, and Chun-Seok Jeong, “A 5-Gbits Clock- and Data-Recovery Circuit With 1-8-Rate Linear Phase Detector in 0.18um CMOS Technology,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 56, no. 1, pp. 6–10, Jan. 2009. [25]S. Byun, J. C. Lee, J. H. Shim, K. Kim, and H.-K. Yu, “A 10-Gb/s CMOS CDR and DEMUX IC with a Quarter-rate Linear Phase Detector,” IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2566–2576, Nov. 2006. [26]Seong-Jun Song, Sung Min Park, Hoi-Jun Yoo, “A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp.1213 – 1219, July 2003. [27]Rogers, J.E, Long, J.R, “A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-/spl mu/m CMOS,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1781 – 1789, Dec. 2002. [28]Rainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama, and Hubert Siedhoff, “A 10-Gb/s CMOS Clock and Data Recovery Circuit With an Analog Phase Interpolator,” IEEE J. Solid-State Circuits, vol. 40, no. 3 , pp. 736 – 743, March 2005. [29]Fuji Yang, Jay H. O’Neill, David Inglis, and Joseph Othmer, “A CMOS Low-Power Multiple 2.5–3.125-Gb/s Serial Link Macrocell for High IO Bandwidth Network ICs,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp.1813 – 1821, Dec. 2002. [30]Rong-Jyi Yang, Shang-Ping Chen, Shen-Iuan Liu, “A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet,” IEEE J. Solid-State Circuits, vol. 39, no. 8, pp.1356 – 1360, Aug. 2004. [31]Chi-Nan Chuang, and Shen-Iuan Liu, “A 0.5–5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 54, no. 11, pp. 939–943, Nov. 2007. [32]Kyunghoon Chung, Jabeom Koo, Soo-Won Kim, and Chulwoo Kim , “An Anti-Harmonic, Programmable DLL-Based Frequency Multiplier for Dynamic Frequency Scaling, ” Asian Solid-State Circuits Conference, 2007. [33]Eunseok Song, Seung-Wook Lee, Jeong-Woo Lee, Joonbae Park, and Soo-Ik Chae, “A Reset-Free Anti-Harmonic Delay-Locked Loop Using a Cycle Period Detector, ” IEEE J. Solid-State Circuits, vol. 39, no.11, pp. 2055–2061, Aug. 2004. [34]Byung-Guk Kim and Lee-Sup Kim, “A 250-MHz–2-GHzWide-Range Delay-Locked Loop, ” IEEE J. Solid-State Circuits, VOL. 40, NO. 6, , pp. 1310–1321, JUNE 2005 [35]J.-H. Kim, Y.-H. Kwak, M. Kim, S.-W. Kim, and C. Kim, “A 120-MHz-1.8-GHz CMOS DLL-based clock generator for dynamic frequency scaling,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp.2077–2082, Sep. 2006 [36]Q. Du, J. C. Zhuang, and T. Kwasniewski, “A low-phase noise, antiharmonic programmable DLL frequency multiplier with period error compensation for spur reduction,” IEEE Trans. Circuits Syst. II, Exp.Briefs, vol. 53, no. 11, pp. 1205–1209, Nov. 2006. [37]Sunghwa Ok, Kyunghoon Chung, Jabeom Koo, and Chulwoo Kim, “An Anti-Harmonic, Programmable DLL-Based Frequency Multiplier for Dynamic Frequency Scaling,” IEEE Transaction on VLSI System, vol. 18, no. 7, pp. 1130–1134, July.2010. [38]Y. Moon, J. Choi, K. Lee, D. K. Jeong, and M. K. Kim, “An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 377 - 384, Mar. 2000. [39]D. J. Foley and M. P. Flynn, “CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated unable oscillator,” IEEE J. Solid-State Circuits, vol. 36, pp. 417–423, Mar. 2001. [40]Y. Okuda, M. Horiguchi, and Y. Nakagome, “A 66–400 MHz adaptive-lock-mode DLL circuit duty-cycle error correction,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 37–38, June 2001. [41]B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000 [42]R. E. Best, Phase-Locked Loops: Theory, Design and Applications.New York: McGraw-Hill, 1998. [43]'HDMI Specification 1.3a', HDMI Licensing, LLC.. 2006-11-10. Retrieved 2009-11-18. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/30663 | - |
| dc.description.abstract | 近年來隨著市場對通訊的需求越來越高，對高速和高整合密度之有線通訊系統的需求和應用與日俱增。所以本篇論文將介紹以延遲鎖定迴路為基底之時脈產生器的設計與實作。由於有線通訊系統的操作(或參考)頻率會因應用而不同，為了支援更多的應用操作範圍應盡可能加大。然而一般以相位鎖定迴路組成的頻率合成器較難以針對大範圍的參考頻率作出最佳化，甚至會有抖動累積及不穩定的現象。本論文中為了改進以上問題，以延遲鎖定迴路為基底之時脈產生器的架構與應用將被提出。
首先，使用 0.18-μm CMOS 製程的延遲鎖定迴路為基底之時脈與資料回復器架構被提出。透過延遲鎖定迴路產生多相位訊號，進而產生五倍於參考頻率的時脈。而且因為利用提出的半速率相位偵測器，在控制路徑上的速度可以降低，取樣誤差及電路負載可以改善。測試電路架構以及部分電路的設計會提出說明，測量結果也被闡述。 接著，包含抗諧波鎖定的以延遲鎖定迴路為基底之倍頻器被呈現。由於使用了無需重置的相位比較器，在頻率改變時仍然可以正確且快速的鎖定。此外，使用的單端延遲電路及轉態偵測電路可以有效的避免倍頻訊號因訊號週期不同造成的誤差。此電路使用 0.18-μm CMOS 製程實作並且加以量測。 | zh_TW |
| dc.description.abstract | With the evolution and scaling down of CMOS technologies, the demand and applications for high-speed and high integration density wire-line communication system has recently grown exponentially. Hence, this thesis illustrates the implementation of the delay-locked loops (DLLs) based clock generator. Because of the operating frequency (or reference frequency) of wire-line communication system depends on the application. The range of operating frequency should be enlarged for more applications. However, the conventional phase-locked loops (PLLs) based frequency synthesizers are hard to optimize for wide reference range, and moreover, the issue of jitter accumulation and stability. Architecture and application about the proposed DLL-based clock generator are presented in order to solve problems that mentioned before.
Firstly, a DLL-based clock and data recovery (CDR) architecture implemented with 0.18-μm CMOS process is presented. Using the DLL for generate multi-phase signals. Then, synthesize the signal that multiplies the reference frequency by five. Furthermore, using the proposed half rate phase detector (PD), the speed on controlled-line can be lowered; the error and loading can be improved. The test circuit and building block circuit design are illustrated, and the measurement results are also described. In the second work, a DLL-based frequency multiplier with anti-harmonic locking technique is proposed. With the anti-harmonic PD, when the operating frequency changing the PD can lock correctly in continues time. Moreover, the single-ended delay cell and transition detector can prevent the error by duty cycle distortion. Implemented with standard TSMC 0.18-μm CMOS process, a DLL-based frequency multiplier is proposed and the measurement results are also demonstrated. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T02:11:38Z (GMT). No. of bitstreams: 1 ntu-100-R97943016-1.pdf: 2130262 bytes, checksum: 0092a595c96e804799573e465c4db0a9 (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | Acknowledgement .....................................I
Abstract .....................................III Table of Contents.....................................VII List of Figures .....................................XI List of Tables.....................................XV Chapter 1 Introduction.....................................1 1.1 Motivation.....................................1 1.2 Organization of This Thesis.....................................2 Chapter 2 Background.....................................5 2.1 Basic Concept of DLL-based and PLL-based Clock Generator.....................................5 2.2 Building Block of the DLL.....................................7 2.2.1 Voltage-Controlled Delay Line (VCDL) .....................................7 2.2.2 Phase Detector (PD) .....................................9 2.2.3 Charge Pump (CP) .....................................11 2.3 Jitter.....................................12 2.3.1 Definition of jitter.....................................12 2.3.2 Source of jitter.....................................14 2.3.3 Jitter in wire-line communication system.....................................18 2.3.4 Jitter measurement.....................................19 2.4 Techniques of DLL-based Frequency Multiplication.....................................20 2.4.1 Edge Combiner.....................................20 2.4.2 Multiplying DLL.....................................22 Chapter 3 A Clock and Data Recovery with DLL-based Clock Generator.....................................25 3.1 Introduction.....................................25 3.2 The Proposed CDR Architecture.....................................26 3.2.1 Introduction of High-Definition Multimedia Interface (HDMI).....................................27 3.2.2 Proposed DLL-based CDR Architecture with Test Circuit.....................................30 3.3 Circuit Implementation.....................................31 3.3.1 Proposed Half-Rate Phase Detector.....................................31 3.3.2 Delay Cell and Voltage-Controlled Delay Line.....................................33 3.3.3 Charge Pump Circuit and Loop Filter.....................................34 3.3.4 Frequency Multiplier.....................................35 3.3.5 Phase Interpolator.....................................36 3.3.6 Pseudo-Random Bit Sequence (PRBS) Generator.....................................38 3.3.7 Simulation Results.....................................38 3.4 Experimental Results.....................................40 3.5 Summary.....................................43 Chapter 4 A Small-Area Anti-Harmonic Locking DLL-Based Frequency Multiplier.....................................45 4.1 Introduction.....................................46 4.2 The Proposed DLL-based Frequency Multiplier Architecture with Anti-Harmonic Locking Phase Detector.....................................47 4.2.1 Harmonic Locking and Stuck Locking.....................................47 4.2.2 Proposed DLL-based Frequency multiplier Architecture.....................................49 4.2.3 Proposed Anti-Harmonic Locking Phase Detector.....................................50 4.3 Circuit Implementation.....................................52 4.3.1 Delay Cell and Voltage-Controlled Delay Line.....................................52 4.3.2 Transition Detector.....................................53 4.3.3 Edge Combiner.....................................55 4.3.4 Charge Pump and Loop Filter.....................................56 4.3.5 Simulation Result.....................................56 4.4 Experimental Results.....................................57 4.5 Summary.....................................63 Chapter 5 Conclusion.....................................65 Bibliography.....................................67 | |
| dc.language.iso | en | |
| dc.subject | 倍頻器 | zh_TW |
| dc.subject | 抗諧波鎖定相位偵測器 | zh_TW |
| dc.subject | 延遲鎖定迴路 | zh_TW |
| dc.subject | Frequency multiplier | en |
| dc.subject | Anti-harmonic locking phase detector | en |
| dc.subject | Delay-locked loop | en |
| dc.title | 以延遲鎖定迴路為基底之時脈產生器設計與實作 | zh_TW |
| dc.title | Design and Implementation of Delay-locked Loop Based Clock Generator | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 鄭裕庭,黃俊郎 | |
| dc.subject.keyword | 延遲鎖定迴路,倍頻器,抗諧波鎖定相位偵測器, | zh_TW |
| dc.subject.keyword | Delay-locked loop,Frequency multiplier,Anti-harmonic locking phase detector, | en |
| dc.relation.page | 70 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2011-08-02 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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