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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Wei-Shun Chuang | en |
| dc.contributor.author | 莊惟舜 | zh_TW |
| dc.date.accessioned | 2021-06-13T02:11:01Z | - |
| dc.date.available | 2007-07-23 | |
| dc.date.copyright | 2007-07-03 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-06-24 | |
| dc.identifier.citation | [Edirisooriya 95] S. Edirisooriya, and G. Edirisooriya, “Diagnosis of Scan Path Failures,” Proc. IEEE VLSI Test Symp., pp. 250-255, 1995.
[Guo 01] R. Guo, and S. Venkataranman, “A Technique for Fault Diagnosis of Defects in Scan Chains,” Proc. IEEE Int’l Test Conf., pp. 268-277, 2001. [Guo 02] R. Guo, and S. Venkataranman , “A New Technique for Scan Chain Failure Diagnosis,” Proc. Int’l Symp. Testing and Failure Analysis, pp. 723-732, 2002. [Hirase 99] J. Hirase, N. Shindou, and K. Akahori, “Scan Chain Diagnosis Using IDDQ Current Measurement,” Proc. Asian Test Symp. pp. 153-157, 1999. [Huang 03] Y. Huang, W.-T. Cheng, S. M. Reddy, C.-J. Hsieh, and Y.-T. Hung, “Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault,” Proc. IEEE Int’l Test Conf., pp. 319-327, 2003. [Huang 04] Y. Huang, W.-T. Cheng, C.-J. Hsieh, H.-Y. Tseng, A. Huang, and Y.-T. Hung, “Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis”, Proc. IEEE Design, Automation, & Test in Europe Conf., pp. 1530-1591, 2004 [Huang 05] Y. Huang, W.-T. Cheng, and J. Rajski, “Compressed Pattern Diagnosis for Scan Chain Failures,” Proc. IEEE Int’l Test Conf., paper 30.3, 2005. [Huang 06] Y. Huang, W.-T. Cheng, N. Tamarapalli, J. Rajski and R. Klingenberg, “Diagnosis with Limited Failure Information,” Proc. Int’l Tes Conf., Oct. 2006. [Kao 06] Yu-Long Kao, Wei-Shun Chuang, and J. C-M Li, “Jump Simulation: A Fast and Precise Scan Chain Fault Diagnosis Technique, “ Proc. Int’l Test Conf., Oct. 2006. [Kibarian 05] J. Kibarian, “The Nature of Yield Ramping: Keeping Ahead of Evolution,” keynote speech, IEEE Int’l Test Conference, 2005. [Koenemann 04] B. Koenemann, “Test In the Era of 'What You see Is NOT What You Get”, ' keynote speech, IEEE Int’l Test Conference, 2004. [Koren 96] I. Koren, Z. Koren, and C. H. Stapper,”A statistical study of defect maps of large area VLSI IC's,” IEEE Trans. VLSI Syst., vol.2, no.2, pp.249-56, 1996. [Kruseman 04] B. Kruseman, A. Majhi, C. Hora, S. Eichenberger, J. Meirlevede, “Systematic Defects in Deep Sub-Micron Technologies,” Proc. IEEE Int’l. Test Conf., pp. 290-298, 2004. [Kundu 94] S. Kundu, “Diagnosis Scan Chain Faults,” IEEE Trans. VLSI Syst., pp. 512-516, 1994. [Lee 91] H. K. Lee and D. S. Ha, “On the Generation of Test Patterns of Combinational Circuits,” Technical Report, No 12-93, Dept. of Electrical Eng. Virginia Polytechnic Institute and State University, 1991. [Li 00] J. C-M Li and E. J. McCluskey, “Testing and Diagnosis of Stuck and Resistive Open Defects, “ Proc. Int’l Test Conf., Oct. 2000. [Li 05a] J. C.-M. Li, “Diagnosis of Single stuck-at Faults and Multiple Timing Faults in Scan Chains, “ IEEE Trans. on VLSI Systems, Vol.13, No. 6, June, 2005, pp. 708-718. [Li 05b] J. C.-M. Li, “Diagnosis of Multiple Hold-time and Setup-time Faults in Scan Chains,” IEEE Trans. on Computers, Vol. 54, No. 11, 2005, pp. 1467-1472. [Narayanan 97] S. Narayanan and A. Das, “An Efficient Scheme to Diagnose Scan Chains,” Proc. IEEE Int’l Test Conf., pp.704-713, 1997. [Nigh 98] P. Nigh, D. Vallett, A. Patel and et. al., “Failure Analysis of Timing and IDDq Failures from the SEMATECH Test Methods Experiment,“ Proc. IEEE Int’l. Test Conf., pp.43-52 , 1998. [Pradhan 86] D. K. Pradhan (editor), Fault Tolerant Computing: Theory and Techniques, Prentice Hall, 1986. [Schafer 92] J. Schafer, F. Policastri and R Mcnulty, “Partner SRLs for Improved Shift Register Diagnostics,” Proc. IEEE VLSI Test Symp., pp. 198-201, 1992. [Song 04] P. Song, F. Stellari, T. Xia, and A. Weger, “A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current,” Proc. IEEE Int’l. Test Conf., pp. 140-147, 2004. [Stanley 01] K. Stanley, “High-Accuracy Flush-and-scan Software Diagnostic,” IEEE Des. Test. Comput., pp. 56-62, Nov-Dec, 2001. [Tzeng 07] C.-W. Tzeng and S.-Y. Huang, “Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in A Scan Chain,” IEEE Trans. on Circuit and Systems II, vol.54, issue 5, 2007 [Wu 98] Y. Wu, “Diagnosis of Scan Chain Failures,” Int’l Symp. On Defect and Fault Tolerance in VLSI systems, pp. 217-222, 1998. [Yang 05] J.-S. Yang and S.-Y. Huang, “Quick Scan Chain Diagnosis Using Signal Profiling, “ Proc. Int’l Conf. on Computer Design, Oct. 2005. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/30642 | - |
| dc.description.abstract | 本論文提出一個掃描鏈診斷技術可定位掃描鏈上的多重時序錯誤。跳躍模擬是一種新穎的平行模擬技術，儘管時序錯誤之間會產生互動，此技術仍能快速找出每個個別錯誤的上邊界及下邊界。此項技術只需要一般的自動測試向量即可，不需要特殊的診斷向量，使得這項技術對生產測試環境上的診斷非常有用。在ISCAS’89基準電路的實驗顯示，即使在一條超過八百個掃描細胞的掃描鏈上有十六個保持時間錯誤，此項技術能夠相當成功的指出幾乎每個錯誤的位置。當錯誤資料相當有限或是錯誤叢聚在一起時，本論文提出的技術仍然十分有效。 | zh_TW |
| dc.description.abstract | This thesis presents a diagnosis technique to locate multiple timing faults in scan chains. Jump simulation is a novel parallel simulation technique which quickly searches for the upper and the lower bounds of every individual fault, in spite of the interaction of multiple faults. This technique requires only regular ATPG patterns, not specialized diagnosis patterns, which make it very useful for diagnosis in the production test environment. Experiments on ISCAS’89 benchmark circuits show that, this technique can successfully pinpoint almost every one of sixteen hold-time faults in a scan chain of more than 800 scan cells. The proposed technique is still effective when the failure data is limited or the faults are clustered. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T02:11:01Z (GMT). No. of bitstreams: 1 ntu-96-R94943155-1.pdf: 543108 bytes, checksum: 45a08df14c10779de5c1443a7df43c4d (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | 摘要 I
Abstract II Table of Contents III List of Figures V List of Tables VII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Jump Simulation for Scan Chain Diagnosis 3 1.3 Contributions 4 1.4 Organization 5 Chapter 2 Background and Previous Work 7 2.1 Previous Works 8 2.2 Definitions 17 2.3 Jump Simulation for Single Fault Diagnosis 23 Chapter 3 Jump Simulation for Multiple Timing Fault Diagnosis 28 3.1 Overall Diagnosis Flow 29 3.2 UB Jump Simulation 31 3.3 Update UB 38 3.4 LB Jump Simulation 40 3.5 Update LB 41 3.6 SO Observation 43 3.7 Exhaustive Simulation 47 Chapter 4 Experimental Results 51 4.1 HT Fault 53 4.2 Five Types of Timing Faults 55 4.3 BR vs. Patterns and BR vs. Simulations 58 4.4 Limited Failure Data 60 4.5 Clustered Faults 61 Chapter 5 Discussions and Future Work 64 5.1 Discussions 64 5.1.1. Intermittent Faults 64 5.1.2 Multiple Faulty Chains 65 5.1.3 Inversions in Scan Chains 65 5.2 Future Work 66 5.2.1 X-filling to Improve Diagnosis Resolution 66 5.2.2 Generalized Exhaustive Simulation 67 Chapter 6 Summary 68 References 69 | |
| dc.language.iso | en | |
| dc.title | 多重掃描鏈時序錯誤診斷 | zh_TW |
| dc.title | Diagnosis of Multiple Scan Chain Timing Faults | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃錫瑜(Shi-Yu Huang),李進福(Jin-Fu Li) | |
| dc.subject.keyword | 掃描鏈,錯誤診斷,自動向量產生, | zh_TW |
| dc.subject.keyword | Fault diagnosis,ATPG,scan chain, | en |
| dc.relation.page | 71 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2007-06-26 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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