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標題: | CMOS 單晶片分數型鎖相迴路頻率合成器之設計與應用 The Design and Application of CMOS Fully-Integrated PLL-Based Fractional-N Frequency Synthesizers |
作者: | Yu-Che Yang 楊育哲 |
指導教授: | 呂學士 |
關鍵字: | 鎖相迴路,頻率合成器,分數型,三角積分調變器,射頻,積體電路, phase-locked loop,frequency synthesizer,delta-sigma,fractional-N,radio-frequency,IC, |
出版年 : | 2007 |
學位: | 博士 |
摘要: | 傳統的整數型頻率合成器會遇到幾個基本的取捨問題,像是頻率解析度和迴路頻寬的取捨,頻率解析度和相位雜訊的取捨,頻率解析度和參考信號突波的取捨。由於整數型合成器的輸出頻率一定是輸入頻率的整數倍,因此這些參數之間的關係是無法改變的,也因此頻率合成器的特性便會受到許多的限制。為了解決這些問題,各式各樣的分數型頻率合成器就被發明了出來。由於在分數型的架構當中,輸出頻率不再是輸入頻率的整數倍,整數型頻率合成器的限制也就可以被打破了。在這些分數型的架構當中,三角積分分數型頻率合成器是最常被使用的一種架構,因為它的分數突波較小,且三角積分調變器具有將量化雜訊移往高頻去的特性。但是分數突波和量化雜訊仍然是分數型頻率合成器設計當中兩個最主要的問題。
量化誤差引起的相位雜訊使得我們必須縮小鎖相迴路的頻寬,因此會造成所謂的雜訊和迴路頻寬的取捨。為了解決這個問題,在本篇論文當中,我們提出一個降低量化雜訊的方法,它是利用降低除頻器解析度的技巧來達成的。根據量測結果顯示,這個技巧可以降低量化雜訊所造成的相位雜訊達6 dB之多,此外實驗也證實了量化雜訊和量化程度之間的關係:量化雜訊正比於量化程度。 在這篇論文中,我們也設計了一個符合多標準數位電視接收器的頻率合成器。多標準的頻率合成器有幾個設計上的困難,第一,它要涵蓋很大的頻率範圍。第二,它有好幾種通道頻寬。最後,它的相位雜訊要求頗嚴格。要達到這些要求,通常的作法是使用兩到三個壓控震盪器,但是這麼做會讓晶片面積變大,功率消耗變高,並不是一個令人滿意的作法。我們提出來的架構是使用分數型的頻率合成器來降低相位雜訊,並同時達到通道頻寬的要求。此外,我們僅僅使用一個壓控震盪器,讓他震盪在較高的頻率上,再利用一個選頻除頻器將壓控震盪器的頻率對應到所需要的頻帶上。這個頻率合成器是利用台積電0.13-um CMOS的製程來設計製作,它的面積很小,只有0.54 mm2,同時消耗的功率也小,在操作電壓為1.2 V的情況下,消耗的功率是16.8 mW. 這本論文的第八章介紹我們提出的另一個量化雜訊推移技術。這個技術藉由加快三角積分調變器的操作頻率來將量化雜訊移到較高的頻率上,再利用鎖相迴路本身低通的特性,進一步的把量化雜訊移除。同時,這個技術不會增加相頻偵測器的比較頻率,因此鎖相迴路的增益不會增加,可以降低迴路頻寬內的相位雜訊。實驗結果顯示,和其他擁有相同相頻偵測器比較頻率的頻率合成器比較,使用這個技術,頻寬內的相位雜訊可以降低12 dB,同時頻寬外的相位雜訊可以降低超過15 dB。 Conventional integer-N frequency synthesizers suffer from fundamental tradeoffs among frequency step size, loop bandwidth, phase noise, and reference spurs. Since the output frequency is an integer multiple of the input frequency, it is impossible to decouple the ties among these parameters and the performances of the synthesizer are thus limited. To resolve these problems, various kinds of fractional frequency synthesizers have been proposed and because they can generate fractional division ratio, the tradeoffs in integer-N synthesizers can thus be removed. Among these structures, the ΔΣ fractional-N frequency synthesizer, for its lower spurs magnitude and high-pass noise shaping ability, is most often adopted. However, the quantization phase noise and fractional spurs still limit the performance of fractional-N synthesizers. Quantization induced phase noise results in the noise-bandwidth tradeoff in a ΔΣ fractional-N frequency synthesizer, which substantially reduces the maximum bandwidth and limits the performances of the frequency synthesizer. In this dissertation, a quantization noise suppression technique, which is based on the reduction in the frequency step size of the frequency divider, is proposed. Measurement results show that by using the proposed technique, the quantization phase noise can be lowered by 6 dB. Besides, the experimental results also show that the quantization phase noise is proportional to the quantization level. In this dissertation we also present a multi-standard fractional-N frequency synthesizer for digital TV tuners. Multi-standard DTV frequency synthesizers have several design challenges, such as wide tuning range, various channel spacing, and low phase noise. To fulfill these requirements, one usually has to use two or three VCOs in a frequency synthesizer. Nevertheless, doing so increases the power consumption and chip area, which is not a satisfactory solution. Our proposed synthesizer makes uses of the fractional-N structure to achieve low in-band phase noise and small channel spacing. On the other hand, only one VCO oscillating at higher frequency and divided down by the band-selecting divider is used to save power consumption and chip area. This synthesizer is design in the TSMC 0.13-um CMOS process and occupies an area of only 0.54 mm2 while consumes a power of only 16.8 mW from a 1.2-V power supply. In Chapter 8 of this dissertation, a quantization noise pushing technique is presented. This technique increases the operating frequency of the ΔΣ modulator so as to move the quantization noise to a higher frequency and thus it can be further suppressed by the PLL. Meanwhile, the comparison frequency of the PFD will not be increased, so that the PLL loop gain can be kept small and decreases the in-band phase noise. The experimental result show that the in-band phase noise can be lowered by 12 dB while the out-of-band phase noise can be reduced by more than 15 dB compared with the synthesizers having the same PFD comparison frequency. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/30178 |
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顯示於系所單位: | 電子工程學研究所 |
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