適用於超寬頻之再生式頻率合成

Abstract

無線通訊的蓬勃發展帶來了人們對於傳輸速率的極大需求，傳統上使用改善信號雜訊比的方式來增加傳輸通到容量已出現瓶頸，新世代的無線通訊系統開始探討如何以增加傳輸頻寬的方式來達到容量的增加。以寬頻的方式做為無線傳輸可能需要多個載波以根據不同的通道特性機動性的調整載波頻率，則傳收機必須快速的切換內部載波產生機制，以選擇所採用的通道。本論文以多頻帶正交分頻多工之超寬頻無線通訊系統作為參考的系統，討論快速頻率切換合成的電路架構。 為達到寬頻的直接頻率合成，文中討論了除頻器電路的非線性操作模式，並且提出了新的半動態除頻器電路，其乃基於再生式調變機制，自一周期性輸入信號萃取出分數頻率成分。其中所構成的電路單元，包括單邊帶混頻器、電流模式邏輯架構之除頻器，其所操作的原理將以新提出的非線性觀點進行分析探討。電流模式邏輯架構之除頻器以狀態空間原理分析，歸納出其具有兩種除頻的操作模式，分別是注入式鎖頻及靜態除頻，此兩種模式將根據系統方程式的特徵值做區分與討論。 此所提出的再生式除頻器架構將應用在直接降頻接收機的載波頻率合成器中使用，其乃採用直接頻率合成方式，以單邊帶混頻器將一個基本頻率移轉一個頻率位移量至所需要的頻率上。在多頻帶正交分頻多工之超寬頻無線通訊系統第一操作模式下，提出了以中間頻帶載波，用3.96GHz為基本頻率方式，以0.18微米的1P6M CMOS製程實現一頻率合成器，此電路達-15dBc的邊帶干擾信號，其使用1.8V的電壓供應，消耗9mA的電流。此外亦提出另一個合成器，以最高頻帶載波，用4.488GHz為基本頻率方式，以次諧波混頻器方式產生直接頻率合成以降低電路之操作頻率，此電路以相同的製程實現，其達-20dBc的邊帶干擾，包含一個環狀震盪器，使用1.8V電壓供應，消耗34mW的功率。 繼而提出擴展至全部14個載波頻率的合成方式，根據該系統跳頻的方式，在一個使用時段僅於三個頻帶間跳動，故本設計提出切換式基本頻率的產生機制來執行每個頻帶群組的跳頻載波。對應於五個頻帶群組的中心載波位於3.96GHz、5.544GHz、7.128GHz、8.712GHz和10.296GHz將從內部的7.92GHz正交性震盪器合成出，並被採用來做為機動性的基本頻率，以執行直接頻率合成。其所對應的電路將適時的打開與關閉，以節省不必要的電流浪費。此頻率的規劃遇到三階諧波干擾的作用，將會在頻率移轉的過程中產生干擾信號。因此將提出有效解決的諧波濾除單邊帶混頻器來執行頻率移轉動作。本設計以0.13微米CMOS製程，於模擬上對於14個載波頻率生成均有-30dBc以上的干擾信號抑制。由於適時的開關內部電路原件，功率消耗可達100mW以下，並且該電路僅使用被動電感原件於震盪器電路與合成器輸出，僅需1120um乘上580um的面積。 為更進一步的降低多載波之寬頻信號接收機制的功率消耗，將提出另一個降頻方式，此乃根據兩個跳動的本地震盪信號來執行降頻的動作。第一個跳頻本地震盪信號將引出一個全新的多模態次諧波雙閘極混頻器電路架構，其所需要的多相位震盪信號將由一切換式相位內插器達成。該電路由90奈米CMOS電路完成，對於14個頻帶的降頻動作功率消耗低於100mW，由於採無電感方式，此設計僅占面積290um乘上460um。

Wireless communication has been in the demand to increase the transmission data rate. Since it is difficult to increase the channel capacity through the signal-to-noise ratio, it is expected to explore new techniques to use wide bandwidth for the wireless communication. The wideband systems may require several carrier frequencies to adaptively convey the data through different channels. The transceiver has to be able to rapidly select the adopted channel with the agile carrier generation mechanism. This thesis takes the multi-band orthogonal frequency division multiple-access (MB-OFDM) ultra-wideband (UWB) system as the reference to discuss the architecture of fast switching frequency conversion. To achieve wide frequency range direct frequency synthesis, the nonlinear circuit operation of the frequency divider circuits is discussed and the semi-dynamic frequency divider is proposed. It uses the regenerative modulation method to extract the fractional frequency from a periodic input signal. The detailed operation of the composing units, the single side-band (SSB) mixers and the current mode logic (CML) frequency dividers, are examined with the new perspectives on their nonlinear operation. The CML frequency divider is analyzed in its state space and the two operation modes, namely the injection lock and the static division, are specified according to the eigenvalues in its system equations. With the aid of the proposed regenerative frequency divider, the carrier generation circuits have been designed for the direct conversion receiver. Using the SSB mixer to synthesize the carrier signal, the direct frequency synthesizer circuits with the center and corner base-tone mechanisms are presented for the mode-1 operation of the MB-OFDM system. The circuit based on the center base-tone at 3.96-GHz has been realized in 0.18um 1P6M CMOS technology and achieves -15dBc spurious performance. It consumes 9mA from the 1.8-V supply. The other circuit is based on the corner base-tone at 4.488-GHz and takes subharmonic mixer for the carrier generation in order to lower the circuits' operating frequencies. It achieves -20dBc spurs and consumes 34mW, including a ring oscillator and the buffer, from the 1.8-V supply using the same technology. The extension to the design for all-band 14 carrier generation has been proposed. According to the frequency hopping mechanism that uses three sub-bands at a time, the base-tone generation for the direct frequency synthesizer is designed to retrieve the base-tone frequencies at 3.96-GHz, 5.544-GHz, 7.128-GHz, 8.712-GHz and 10.296-GHz from the 7.92-GHz quadrature voltage controlled oscillator (QVCO) and adaptively switch on and off the circuit blocks in order to achieve low power consumption. It is observed that the third harmonic components from the large input deviations cause more spurious signals than the image effect in the frequency translation process. The harmonic rejection single side-band mixer architecture is proposed to suppress this effect. In 0.13um CMOS realization, the simulation results show that the synthesizer achieves -30dBc spurious response in the 14 modes of carrier generation. The power consumption is less than 100mW for the switching mechanism inside the circuit blocks. The circuit only uses the on-chip inductors for the oscillator core and the hopping carrier output. It takes 1120um x 580um chip area to accommodate the whole frequency processing units. To further reduce the power consumption in the reception mechanism for wideband signals with multiple carriers over wide frequency range, another method to perform the down-conversion is proposed. It uses two hopping local oscillation signals to perform the frequency conversion. The first hopping local oscillation signal explores the harmonically related frequency steps while the second hopping local oscillation signal is derived from the oscillator through a nested regeneration loop. The first downconversion uses the proposed multi-subharmonicity dual-gate mixer to perform a multi-harmonic frequency down conversion. The switched phase interpolator is built to supply the multiphase LO signals for the multi-mode operation. The simulated performance shows that the circuit in 90nm CMOS technology performs the 14-band frequency conversion using one oscillation frequency with the power consumption less than 100mW. The inductorless design achieves 290um x 460um area.