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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | I-Ching Chen | en |
| dc.contributor.author | 陳翊青 | zh_TW |
| dc.date.accessioned | 2021-06-13T01:12:04Z | - |
| dc.date.available | 2008-07-24 | |
| dc.date.copyright | 2007-07-24 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-07-18 | |
| dc.identifier.citation | [1] B.Razavi, “Principles of Data Conversion System Design” Wiley-IEEE Press, 1995
[2] Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters” Kluwer Academic Publishers, 2003 [3] K. Kusumoto, K. Murata, A. Matsuzawa, S. Tada, M. Maruyama, K. Oka, and H. Konishi, “A 10b 20MHz 30mW Pipelined Interpolating CMOS ADC,” IEEE International Solid-State Circuits Conference, pp. 62-63, Feb. 1993 [4] Pedro M. Figueiredo, Paulo Cardoso, Ana Lopes, Carlos Fachada, Naoyuki Hamanishi, Ken Tanabe and Joao Vital “A 90nm CMOS 1.2V 6b 1GS/s Two-Step Subranging ADC” Digest of Technical Papers. ISSCC 2006 IEEE International Pages:568-673 [5] Chien-Kai Hung, Jian-Feng Shiu, I-Ching Chen and Hsin-Shu Chen “A 6-bit 1.6GS/s Flash ADC in 0.18-um CMOS with Reversed-Reference Dummy” IEEE Solid-State Circuits Conference, 2006 ASSCC, pages:335-338, Nov. 2006 [6] M. Flynn and D. Allstot, “CMOS Folding A/D Converters with Current-Mode Interpolation,” IEEE J. Solid-State Circuits, vol.31, pp. 1248-1255, Sep. 1996 [7] Govert Geelen and Edward Paulus “An 8b 600MS/s 200mW CMOS Folding A/D Converter Using an Amplifier Technique” IEEE International Solid-State Circuits Conference, pp. 254-526, Feb. 2004 [8] Kurosawa. N, Kobayashi. H, Maruyama. K, Sugawara. H, Kobayashi. K, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems” Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on Volume 48, Issue 3, March 2001 Pages:261-271 [9] Hendrik van der Ploeg and Robert Remmers “A 3.3-V 10-b 25-MSample/s Two-Step ADC in 0.35-um CMOS” IEEE J. Solid-State Circuits, vol.34, pp. 1803-1811, Dec. 1999 [10] Aida Varzaghani and Chih-Kong Ken Yang “A 600-MS/s 5-Bit Pipeline A/D Converter Using Digital Reference Calibration” IEEE J. Solid-State Circuits, vol.41, pp. 310-319, Feb. 2006 [11] Tatsuji Matsuura, Toshiro Tsukada, Shinya Ohba, Eiki Imaizumi, Hiroshi Sato and Seiichi Ueda “An 8b 20MHz CMOS Half-Flash A/D Converter” IEEE International Solid-State Circuits Conference, pp. 220-221, Feb. 1988 [12] Martin Clara, Andreas Wiesbauer and Franz Kuttner “A 1.8V Fully Embedded 10b 160MS/s Two-Step ADC in 0.18um CMOS” IEEE custom integrated circuits conference pages:437-440 ,2002 [13] Lauri Sumanen, Mikko Waltari and Kari A. I. Halonen “A 10-bit 200-MS/s CMOS Parallel Pipeline A/D Converter” IEEE J. Solid-State Circuits, vol.36, No.7, pp. 1048-1055, July 2001 [14] Krishnaswamy Nagaraj, H. Scott Fetterman, Joseph Anidjar, Stephen H. Lewis and Robert G. Renninger “A 250-mW, 8-b, 52-Msamples/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers” IEEE J. Solid-State Circuits, vol.32, No.3, pp. 312-320, March 1997 [15] Sotirios Limotyrakis, Scott D. Kulchycki, David Su, Bruce A. Wooley “A 150MS/s 8b 71mW Time-interleaved ADC in 0.18um CMOS” IEEE International Solid-State Circuits Conference, pp. 258-526, Feb. 2004 [16] Sang-Min Yoo, Jong-Bum Park, Seung-Hoon Lee and Un-Ku Moon “A 2.5-V 10-b 120-MSample/s CMOS Pipelined ADC Based on Merged-Capacitor Switching” IEEE Transactions on circuits and systems - II : Express Briefs Volume 51, NO.5, MAY 2004 Pages:269-275 [17] X. Jiang, et. Al., “A 2GS/s 6b ADC in 0.18um CMOS,” IEEE Int. Solid-State Conf. Dig. Tech. Papers, Feb. 2003, pp. 322-323 [18] Byung-Moo Min, Peter Kim, Frederick W. Bowman, Ⅲ, David M. Boisvert and Arlo J. Aude “A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC” IEEE J. Solid-State Circuits, vol.38, No.12, pp. 2031-2039, Dec 2003 [19] Koen Uyttenhove, Michel S. J. Steyaert “Speed-Power-Accuracy Tradeoff in High-Speed CMOS ADCs” IEEE Transactions on Circuits and systems-II: Analog and Digital signal processing, vol.49 no.4 April 2002, Pages:280-287 [20] J. Doernberg, H. Lee, and D. A. Hodges, “Full-speed testing of A/D converters,” IEEE J. Solid-State Circuits, vol.19, No.6, pp. 820-827, Dec 1984 [21] Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig and Franz Kuttner “A 6-bit 1.2GS/s Low-Power Flash-ADC in 0.13-um Digital CMOS” IEEE Journal of solid-state circuits, vol.40 no.7 July 2005 pages:1499-1504 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/29608 | - |
| dc.description.abstract | 本研究是採用兩階段式 (Two-step) 的架構，來實現高速的類比數位轉換器(Analog-to-Digital Converter)。在此論文中提出一個快速穩定的方法 (fast-settling method)來縮短運算放大器的上升時間以及經由重新安排時脈圖來使得電路可以工作的更加有效率。本晶片使用台積電0.13-μm CMOS製程製作，解析度為六位元，操作時脈頻率為1 GS/s，INL為+0.3/-0.3 LSB，DNL為+0.49/-0.49 LSB，在輸入信號頻率為奈奎斯特頻率的情況下，SFDR為49.2dB，SNDR為31.3dB，在1.2伏特的供應電壓下，消耗功率為 50mW。 | zh_TW |
| dc.description.abstract | A 1 GS/s 6-bit CMOS two-step ADC using fast-settling method and through timing rearrangement is demonstrated in a standard 0.13-μm CMOS process. The proposed method shortens the slew time of OPAMP in MDAC and the timing arrangement makes the circuits operated more efficient. The prototype circuit exhibits an INL of +0.3/-0.3 LSB and a DNL of +0.49/-0.49 LSB. The SNDR and SFDR achieve 31.3 and 49.2 dB at 1 GS/s for Nyquist input frequency. The ADC consumes 50 mW at 1.2V supply and occupies an active chip area of 0.16 mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T01:12:04Z (GMT). No. of bitstreams: 1 ntu-96-R93943111-1.pdf: 3711023 bytes, checksum: 3c0b79e6feee60238378dc4c22fbcd0d (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | ACKNOWLEDGMENT I
ABSTRACT III TABLE OF CONTENTS Ⅴ LIST OF FIGURES Ⅶ LIST OF TABLES Ⅸ CHAPTER 1 INTRODUCTION 1 CHAPTER 2 FUNDAMENTALS OF ANALOG-TO-DIGITAL CONVERTER 2 2.1 PERFORMANCE METRICS 2 2.1.1 Signal-to-Noise Ratio (SNR) 2 2.1.2 Total Harmonic Distortion (THD) 2 2.1.3 Spurious-Free Dynamic Range (SFDR) 3 2.1.4 Signal-to-Noise and Distortion Ratio (SNDR) 3 2.1.5 Effective Number of Bits (ENOB) 3 2.1.6 Differential Nonlinearity (DNL) 4 2.1.7 Integral Nonlinearity (INL) 5 2.2 HIGH-SPEED AND LOW RESOLUTION ADC ARCHITECTURES 6 2.2.1 Two-step ADC 7 2.2.2 Full flash ADC 8 2.2.3 Folding and Interpolating ADC 9 CHAPTER 3 TIME-INTERLEAVED A/D CONVERTER 12 3.1 INTRODUCTION 12 3.2 TIME-INTERLEAVED A/D CONVERTER 12 3.3 CHANNEL MISMATCH EFFECTS 14 3.3.1 Offset mismatch effect 14 3.3.2 Gain mismatch effects 16 3.3.3 Clock timing error effects 17 3.3.4 Combined channel mismatch effects 18 CHAPTER 4 PROPOSED TIMING DIAGRAM AND FAST-SETTLING METHOD 21 4.1 CONVENTIONAL TWO-STEP ADC TIMING DIAGRAM 21 4.2 PROPOSED TIMING DIAGRAM 23 4.3 FAST-SETTLING METHOD 25 CHAPTER 5 CIRCUIT IMPLEMENTATION 29 5.1 ARCHITECTURE 29 5.2 MDAC 30 5.2.1 Residue of MDAC 32 5.3 OPERATIONAL AMPLIFIER 34 5.4 COMPARATOR 35 5.5 DIGITAL CIRCUIT FOR FAST-SETTLING 37 5.6 BIAS CIRCUIT AND CMFB CIRCUIT 38 5.7 CLOCK GENERATOR 39 5.8 SIMULATION RESULT 41 5.8.1 Operational amplifier simulation 41 5.8.1.1 AC analysis 41 5.8.1.2 Transient analysis 42 5.8.2 FFT test 43 5.8.3 Summary 44 CHAPTER 6 PERFORMANCE 45 6.1 FLOOR PLAN AND LAYOUT CONSIDERATIONS 45 6.2 TEST SETUP 48 6.3 PCB DESIGN 50 6.4 EXPERIMENT RESULT 54 6.4.1 Static performance 55 6.4.2 Dynamic performance 56 6.5 SUMMARY 59 CHAPTER 7 CONSLUSIONS 61 BIBLIOGRAPHY 62 | |
| dc.language.iso | en | |
| dc.title | 一個每秒10億次取樣6位元48毫瓦類比數位轉換器 | zh_TW |
| dc.title | A 1GS/s 6-bit 48mW A/D Converter | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢,顧孟愷,陳怡然,盧奕璋 | |
| dc.subject.keyword | 類比數位轉換器,兩階段式,時間交錯,低功率, | zh_TW |
| dc.subject.keyword | ADC,Two-step,Time-interleave,low power, | en |
| dc.relation.page | 64 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2007-07-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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