請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/29388完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
| dc.contributor.author | Yu-Lin Chen | en |
| dc.contributor.author | 陳育麟 | zh_TW |
| dc.date.accessioned | 2021-06-13T01:05:51Z | - |
| dc.date.available | 2007-07-27 | |
| dc.date.copyright | 2007-07-27 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-07-24 | |
| dc.identifier.citation | [1] P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-Way Multithreaded SPARC Processor. IEEE Computer Society. March-April, 2005. pp. 21-29.
[2] L. Clark, E. Hoffman, J. Miller, M. Biyani, Y. Liao, S. Strazdus, M. Morrow, K. Velarde, and M. Yarch. An Embedded 32-b Microprocessor Core for Low-Power and High-Performance Applications. IEEE Journal of Solid-State Circuits. November 2001. vol. 36, no. 11, pp. 1599-1608. [3] D. Marr, F. Binns, D. Hill, G. Hinton, D. Koufaty, J. Miller, M. Upton. Hyper-Threading Technology Architecture and Microarchitecture. Intel Technology Journal. Q1 2002. pp. 4-15. [4] ARM Architecture Reference Manual, ARM Limited, 2000. [5] Hennessy and Patterson, Computer Architecture - A Quantitative Approach,Morgan Kaufmann, 3/e, 2002. [6] TSMC 0.18μm Process 1.8-Volt SAGE-T Standard Cell Library Databook, Artisan Components Inc, 2003. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/29388 | - |
| dc.description.abstract | 效能是由總處理量來衡量的。總處理量越高，效能就越高。指令層級平行化﹙Instruction-Level Parallelism﹚與執行緒層級平行化﹙Thread-Level Parallelism﹚是兩個主要用來提升微處理器效能的技術。本論文是設計一個與ARM相容的微處理器，其指令層級平行化由6級的管線處理來實現，而執行緒層級平行化則由支援2個fine-grained的多執行緒來實現。為了功率消耗的效率，從架構的階層往下到邏輯閘的階層，有許多設計是與低功率設計有關的。 | zh_TW |
| dc.description.abstract | Performance is measured by throughput. The higher the throughput, the higher the performance. ILP (Instruction-Level Parallelism) and TLP (Thread-Level Parallelism) are two major technologies to improve CPU’s performance. This thesis is to design a 6-stage pipelined ARM-like CPU to fulfill ILP, and then develop it to TLP with a 2-thread fine-grained multithreading. For power efficiency, a lot of work has been done on low power design from architecture level down to gate level. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T01:05:51Z (GMT). No. of bitstreams: 1 ntu-96-R94943112-1.pdf: 1744234 bytes, checksum: e158a9e5d0985de8dc419aecf27ceaad (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | 1 Introduction 1
1.1 Hardware Multithreading ……………………………………………………….. 1 1.2 Software Multithreading ………………………………………………………... 6 2 Specification 8 2.1 Pin Description ………………………………………………………………….. 8 2.2 Programmer’s Model and Register File …………………………...................... 10 2.3 Status Register …………………………………………………………………. 11 2.4 Program and Data Memory ……………………………………………………. 13 2.5 Interrupt Requests ……………………………………………………………... 14 2.6 Multithreading Mechanism ……………………………………………………. 15 2.7 Instruction Queue ……………………………………………………………… 18 2.8 IO Peripheral Devices …………………………………………………………. 18 3 Implementation 20 3.1 Low Power Design …………………………………………………………….. 20 3.2 Chip Pipeline Architecture …………………………………………………….. 22 3.3 Double Edge Trigger Circuit …………………………………………………... 25 3.4 Design Flow …………………………………………………………………… 28 3.5 Implementation Results …………………………………………………………. 28 4 Simulation 30 5 Conclusion 32 Reference 33 | |
| dc.language.iso | zh-TW | |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 多執行緒 | zh_TW |
| dc.subject | 平行化 | zh_TW |
| dc.subject | 微處理機 | zh_TW |
| dc.subject | parallelism | en |
| dc.subject | low power | en |
| dc.subject | microprocessor | en |
| dc.subject | multithreading | en |
| dc.title | 多執行緒微處理器設計 | zh_TW |
| dc.title | Multithreading CPU Design | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 楊佳玲(Chia-Lin Yang),江介宏(Jie-Hong Jiang) | |
| dc.subject.keyword | 多執行緒,平行化,微處理機,低功率, | zh_TW |
| dc.subject.keyword | multithreading,parallelism,microprocessor,low power, | en |
| dc.relation.page | 33 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2007-07-24 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-96-1.pdf 未授權公開取用 | 1.7 MB | Adobe PDF |
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