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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳安宇(An-Yeu Wu) | |
| dc.contributor.author | Yu-Chuan Huang | en |
| dc.contributor.author | 黃裕全 | zh_TW |
| dc.date.accessioned | 2021-06-13T01:03:09Z | - |
| dc.date.available | 2008-07-29 | |
| dc.date.copyright | 2007-07-29 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-07-25 | |
| dc.identifier.citation | References
[1] E. Biglieri, D. Divsalar, P. J. Mclane and M. K. Simon, Introduction to trellis-coded modulation with applications, Maxwell Macmillan, Canada, 1991. [2] S. Lin and D. J. Costello, Jr., Error Control Coding, Prentice-Hall, New Jersey, 1982. [3] R. E. Ziemer, R. L. Peterson, Introduction to Digital Communication, Macmillan, New York, 1992. [4] A. J. Viterbi, “Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm,” IEEE Trans. on Information Theory, Vol. IT-13, pp. 260-269, April 1967. [5] A. J. Viterbi, “Convolutional Codes and Their Performance in Communication Systems,” IEEE Trans. on Communication Technology, Vol. COM-19, pp. 751-772, October 1971. [6] G. D. Forney, “The Viterbi Algorithm,” Proceedings of the IEEE, Vol. 61, pp.268-278, March 1973. [7] G. D. Forney, “Convolutional Codes II: Maximum Likelihood Decoding,” Information and Control, Vol. 25, pp. 222-226, July 1974. [8] Andries P. Hekstra, “An alternative to metric rescaling in Viterbi decoders,” IEEE Trans. on Commu., vol. COM-37, no. 11, pp. 1220-1222, Nov. 1989. [9] C. Shung, P. Siegel, G. Ungerbock, and H. Thapar, “VLSI Architectures for Metric Normalization in the Viterbi Algorithm,” in Proceedings of the IEEE International Conference on Communications, pp. 1723-1728, IEEE, 1990. [10] Ivan M. Onyszchuk, “Truncation Length for Viterbi Decoding,” IEEE trans. on Commu., vol. COM-39, pp. 1023-1026, July 1991. [11] P. J. Black and T. H. Y. Meng, “Hybrid Survivor Path Architecture for Viterbi Decoders,” in Proc. ICASSP 93, 1993, pp. I-433-I-436. [12] J. Sparso, H. J. Jorgensen, E. Paaske, S. Pedersen and T. R. Petersen, “ An Area-Efficient Topology for VLSI Implementation of Viterbi Decoders and Other Shuffle-Exchange Type structures,” IEEE Journal of Solid-State Circuits, vol. 26, no. 2, Feb. 1991. [13] M. Boo, F. Arguello, J. D. Bruguera, R. Doallo and E. L. Zapata, “High-Performance VLSI Architecture for the Viterbi Algorithm,” IEEE Trans. on Commu., Vol. 45, no. 2, Feb. 1997. [14] Y.N. Chang, Hiroshi Suzuki, K. K. Parhi, “A 2-Mb/s 256-State 10-mW Rate-1/3 Viterbi Decoder,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, Jun. 2000. [15] P. J. Black and T. H. Meng, “A 140-Mb/s, 32-state, radix-4 Viterbi de-coder,” IEEE Journal of Solid-State Circuits, vol. 27, pp. 1877–1885, Dec. 1992. [16] (Online) http://www.ieee802.org/16/ [17] (Online) http://www.3gpp.org/ [18] Y. Gang, A. T. Erdogan, and T. Arslan, “An efficient pre-traceback architecture for the Viterbi decoder targeting wireless communication applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vo1. 52, no. 6, pp.1148–1156, Jun, 2005. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/29235 | - |
| dc.description.abstract | 在現今的無線通訊系統中，行動手持設備的應用已經越來越廣泛。同時，使用者對於手持設備資料傳輸的能力以及其訊號接受範圍的需求也日益增加。這樣的趨勢促使適用於廣泛領域的通訊規格及系統快速地發展，例如無線網路通訊系統中的IEEE 802.16(WiMAX)，802.16e(mobile WiMAX)，以及手機通訊系統中的3GPP，HSDPA(high speed downlink packet access)等等。支援多規格的手持通訊系統將是未來的一個趨勢。
在上述的規格中，維特比解碼器都是其通道編解碼器(channel CODEC)中不可獲缺的模組。雖然維特比解碼器的錯誤更正能力比不上近年來快速發展的渦輪解碼器(turbo decoder)以及低密度奇偶校驗解碼器(LDPC)，但其低功率且低硬體資源需求的特性使得維特比解碼器依然被各種先進的通訊規格所採用。因此，在此論文中我們設計出符合多種規格的維特比解碼器。 在本論文中，我們致力於兩個部份。首先，我們針對維特比解碼器中的存活路徑管理單元(survivor memory management unit, SMU)提出了兩種創新的技術，藉此我們可以在沒有錯誤更正效能損失的情況下降低功率消耗以及提高解碼速度。另外，我們提出了支援WiMAX，3GPP，以及HSDPA等多重規格的維特比解碼器架構。在硬體實作上，我們提出的維特比解碼器是透過標準單元的設計流程並利用TSMC 0.13um的先進製程來實現。 | zh_TW |
| dc.description.abstract | The mobile handheld devices have been widely used as the application of the wireless communication systems. The requirement of the data throughput and the effective range of the handheld devices have been increased at the same time. It makes the needs of the long-range communication systems, such as IEEE 802.16 (WiMAX), 802.16e (mobile WiMAX), 3GPP of the mobile communication system, and the HSDPA (high speed downlink packet access), increase rapidly. In order to access different communication systems, the mobile communication devices suitable for multiple standards will be an important trend in the coming future.
In the standards mentioned above, Viterbi decoder is one of the essential modules of the channel CODEC. Though the error correcting performance of the Viterbi decoder may not better than the Turbo or LDPC decoders, Viterbi decoders are still widely adopted in the modern communication systems due to its lower power consumption and lower hardware requirements. As the reasons mentioned above, we propose several techniques for improving the Viterbi decoder and a structure suitable for a multi-mode Viterbi decoder design. In this thesis, we were devoted to two fields. First, we propose two techniques of modifying the structure of the survivor memory units (SMU), which can reduce the power consumption and the decoding latency. Second, we propose a Viterbi decoder structure for fulfilling the specification of the WiMAX, 3GPP, and HSDPA at the same time. We use the 0.13 technology of the cell-based design flow to implement our proposed Viterbi decoder chip. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T01:03:09Z (GMT). No. of bitstreams: 1 ntu-96-J94921030-1.pdf: 1748922 bytes, checksum: 5ee9b43039079eb0c816306357880cf6 (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | Contents
List of Figures ix List of Tables xii Chapter 1 Introduction 1 1.1 Overview of Error-Correcting Codes 1 1.2 Overview of WiMAX & 3G-Based Systems 2 1.3 Motivation & Goal 4 1.4 Thesis Organization 6 Chapter 2 Convolutional Code & the Viterbi Algorithm 7 2.1 Convolutional Codes 7 2.1.1 Definition of a Convolutional Code 8 2.1.2 Trellis Diagram of a Convolutional Code 12 2.1.3 Decoding the Convolutional Codes 14 2.2 Viterbi Algorithm 16 2.2.1 Definition of Viterbi Algorithm 16 2.2.2 An Example of Viterbi Decoding 19 2.2.3 Basic Processing Units of Viterbi Decoders 22 Chapter 3 Proposed Survivor Memory Management Techniques 25 3.1 Register Exchange (RE) Method 26 3.2 Trace-Back (TB) Method 28 3.2.1 Basic Concept 28 3.2.2 Memory & Processor Configuration 31 3.2.3 K-Pointer Architecture 33 3.3 Trace-Forward (TF) Concept [18] 35 3.4 Proposed State Exchange (SE) Method 38 3.4.1 Basic Concept 38 3.4.2 Low Power State Exchange Architecture 41 3.5 Proposed Pipelined Trace-Forward Method 44 Chapter 4 Multi-Mode Viterbi Decoder Architecture 47 4.1 Multi-Mode Branch Metric Unit 49 4.2 Dual-Mode Add-Compare-Select Unit 52 4.3 Dual-Mode Survivor Memory Unit 56 Chapter 5 VLSI Implementation of the Proposed Viterbi Decoder 59 5.1 Fixed Point Simulation 59 5.2 Chip Implementation 62 5.2.1 Design Flow 62 Chapter 6 Conclusions and Future Work 69 6.1 Conclusions 69 6.2 Future Work 70 References 71 | |
| dc.language.iso | zh-TW | |
| dc.title | 適用於無線通訊系統之多模維特比解碼器VLSI設計 | zh_TW |
| dc.title | Multi-Mode Viterbi Decoder VLSI Design for Wireless Communication Systems | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 闕志達(Tzi-Dar Chiueh),顧孟愷(Mong-kai Ku) | |
| dc.subject.keyword | 維特比,解碼器,無線通訊, | zh_TW |
| dc.subject.keyword | Viterbi,WiMAX,3GPP,HSDPA,SMU, | en |
| dc.relation.page | 72 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2007-07-25 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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