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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 蔡坤諭(Kuen-Yu Tsai) | |
| dc.contributor.author | Meng-Fu You | en |
| dc.contributor.author | 游孟福 | zh_TW |
| dc.date.accessioned | 2021-06-13T00:43:33Z | - |
| dc.date.available | 2010-07-26 | |
| dc.date.copyright | 2007-07-26 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-07-23 | |
| dc.identifier.citation | [1] G. E. Moore, Cramming More Components onto Integrated Circuits, Electronics, pp. 114-117, 1965
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Balasinski, A Methodology to Analyze Circuit Impact of Process Related MOSFET Geometry, in Proceedings of the SPIE, Design and Process Integration for Microelectronic Manufacturing, Vol.5379, pp.85-92, 2004 [11] C. Pacha, M. Bach, K. V. Arnim, R. Brederlow, D. S. Lansiedel, P. Seegebrecht, J. Berthold, and R. Thewes, Impact of STI-Induced Stress, Inverse Narrow Width Effect, and Statistical VTH Variations on Leakage Currents in 120nm CMOS, Solid-State Device Research Conference, Proceeding of the 34th European, pp.397-400, 2004 [12] S. D. Kim, H. Wada, and J. C. S. Woo, TCAD-Based Statistical Analysis and Modeling of Gate Line-Edge Roughness Effect on Nanoscale MOS Transistor Performance and Scaling, IEEE Transactions on Semiconductor Manufacturing, Vol.17, No.2, May 2004 [13] ISE TCAD Release 10.0 User’s Manual, 2004 [14] A. Shibkov and V. Axelrad, Integrated Simulation Flow for Self-Consistent Manufacturability and Circuit Performance Evaluation, in Simulation of Semiconductor Processes and Device International Conference, IEEE, 2005 [15] I. Polishchuk, N. Mathur, C. Sandstrom, P. Manos, and O. Pohland, CMOS Vt-Control Improvement through Implant Lateral Scatter Elimination, Semiconductor Manufacturing, IEEE International Symposium, pp. 193-196, 2005 [16] V. Axelrad, A. Shibkov, G. Hill, H. J. Lin, C. Tabery, D. White, V. Boksha, and R. Thilmany, A Novel Design-Process Optimization Technique Based on Self-Consistent Electrical Performance Evaluation, in Proceedings of SPIE, Design and Process Integration for Microelectronic Manufacturing , Vol. 5756, pp. 419-426, May 2005 [17] V. Axelrad, A. Shibkov, and V. Boksha. Integrated Scheme for Yield Improvement by Self-Consistent Minimization of IC Design and Process Interactions, United States Patent Application 20050114822 [18] Y. Trouiller, T. Devoivre, J. Belledent, F. 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Neureuther, From Poly Line to Transistor: Building BSIM Models for Non-Rectangular Transistors, in Proceeding of SPIE Vol.6156, Design and Process Integration for Microelectronic Manufacturing, 2006 [23] P. Gupta, A. Kahng, Y. Kim, S. Shah, and D. Sylvester, Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis, in Proceedings of SPIE Vol.6156, Design and Process Integration for Microelectronic Manufacturing, 2006 [24] S. X. Shi, P. Yu, and D. Z. Pan, A Unified Non-Rectangular Device and Circuit Simulation Model for Timing and Power, ICCAD, pp. 423-428, 2006 [25] Y. S. Su, Apply Control Theories to Improve Optical Proximity Correction Convergence with Design Intent. Master Thesis, National Taiwan University, 2006 [26] M. F. You, Philip CW Ng, Y. S. Su, K. Y. Tsai, and Y. C. Lu., Impacts of Optical Proximity Correction Settings on Electrical Performance, in Proceedings of SPIE vol. 6521, Design for Manufacturability through Design-Process Integration, 2007 [27] R. Singhal, A. Balijepalli, A. Subramaniam, F. Liu, S. Nassif, and Y. Cao, Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation, DAC, 2007 [28] Y. Cao et al., Predictive Technology Model website. Available at http://www.eas.asu.edu/~ptm/ [29] Wikipedia, photolithography article, available at http://en.wikipedia.org/wiki/Photolithography [30] Synopsys company, Proteus, Progen Prospector Full-Chip Optical Proximity Correction, available at http://www.synopsys.com/products/avmrg/proteus_ds.html | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/29157 | - |
| dc.description.abstract | 當積體電路之線寬隨著摩爾定律縮小到次波長等級，非理想之光學效應，例如:光學鄰近效應、像差、繞射等，變得愈來愈嚴重，在半導體微影製程中，即使利用解析度增強技術，這些效應或變異亦將造成矽晶圓上成像之圖形失真。這些非理想的圖形將影響製造出來之元件電氣特性，如驅動電流、漏電流、臨界電壓。現今之電晶體模型無法處理非長方形的閘極形狀。為了分析微影後(post-litho)之電路特性，非長方形電晶體模型(non-rectangular model)是不可或缺的。在本論文裡，我們探討各種非長方形電晶體之模型方法。我們運用元件模擬軟體來檢視窄寬長效應(Narrow width effects)對元件特性的影響，並且驗證等效閘極通道長度(Equivalent gate length)模型方法的精確度。為了增進漏電流分析之準確度，我們提出一個位置相依之權重函數(location-dependent weighting function)來考慮窄寬長效應造成之漏電流變異。最後，我們建立一個結合光學效應與電路特性之模擬流程，運用此模擬流程，我們探討光學鄰近修正(OPC)設定，如修正次數與切割長度，對靜態隨機存取記憶體(6T-SRAM)微影後之電路特性的影響。 | zh_TW |
| dc.description.abstract | As the critical dimension of integrated circuits reduces to sub-wavelength following the path of “Moore’s law”, non-ideal optical effects, such as optical proximity effects, aberration, and optical diffraction, become more serious. Those effects or variations would result in wafer pattern distortions even applying resolution enhancement techniques (RETs). The non-ideal patterning would impact the electrical characteristics of manufactured devices, including drive current (Ion), leakage current (Ioff), and threshold voltage (Vth). Today’s compact transistor models can not handle the non-rectangular gate shape. The model of non-rectangular transistor is indispensable for post-litho circuit simulation. In this thesis, different non-rectangular transistor modeling approaches are discussed. TCAD device simulator is utilized to examine the impacts of narrow width effects on device characteristics. The accuracy of equivalent gate length (EGL) modeling approach is verified based on device simulations. To improve the accuracy for leakage current analysis, a location-dependent weighting function is proposed to take into account the leakage current variation due to narrow width effects. Finally, a post-litho simulation flow that combines the lithographic effects and circuit performance is built. The impacts of OPC settings, including number of corrections and segmentation length, on post-litho circuit performance is discussed based on a 6T-SRAM cell. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T00:43:33Z (GMT). No. of bitstreams: 1 ntu-96-R94921002-1.pdf: 1410551 bytes, checksum: 40a2f7bd369cc6a4011c0bed9ce718d5 (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | Abstract I
摘要 II Statement of Contributions III Acknowledgement IV 誌謝 V Table of Contents VI List of Tables VIII List of Figures IX Chapter 1. Introduction 1 1.1 Optical Lithography 1 1.2 Contributors to Non-Rectangular Wafer Pattern 2 1.3 Optical Proximity Correction (OPC) 2 1.4 Concept of Design for Manufacturability 4 1.5 Scope of Discussion 5 Chapter 2. MOSFET Device Characteristics 7 2.1 MOSFET Structure and Operation 7 2.2 Basic Semiconductor Device Physics 10 Chapter 3. Approaches of Non-Rectangular Transistor Modeling 12 3.1 Narrow-Sliced Transistors of Varying Gate Length in Parallel 12 3.2 Equivalent Gate Length (EGL) Method 13 3.3 Post-Litho Device Modeling Card 14 3.4 Continuously-varying EGL Model 16 Chapter 4. Device Simulation for Verifying the EGL Method 19 4.1 Device Simulation Setup 19 4.2 Impacts of Narrow Width Effects on Device Characteristics 23 4.3 The Accuracy of Conventional EGL Method 25 4.4 Location-Dependent Weightings for Accurate Off Current Estimation 27 4.5 Summary 32 Chapter 5. Impacts of OPC Settings on Circuit Performance 33 5.1 Overall OPC and Circuit Simulation Flow 33 5.2 EGL for Printed Non-Rectangular Transistor Modeling 34 5.3 A 6T-SRAM Circuit Layout for Simulation 35 5.4 Lithography and OPC Settings 37 5.5 Lithography OPC V.S. Geometric Distortion and Circuit Performance 38 5.6 Summary 41 Chapter 6. Conclusions and Future Work 42 Bibliography 43 | |
| dc.language.iso | en | |
| dc.title | 次波長光學微影效應對超大型積體電路之元件與電路特性影響之分析 | zh_TW |
| dc.title | Analysis of Impacts of Subwavelength Lithography Effects on Device Characteristics and Circuit Performance for Nanometer VLSI | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.coadvisor | 盧奕璋(Yi-Chang Lu) | |
| dc.contributor.oralexamcommittee | 陳永耀(Yung-Yaw Chen),張耀文(Yao-Wen Chang),劉如淦(Ru-Gan Liu) | |
| dc.subject.keyword | 微影製程,光學鄰近修正,非長方形電晶體,窄寬長效應,位置相依之權重函數, | zh_TW |
| dc.subject.keyword | Lithography,Optical Proximity Correction,Non-rectangular transistor,Narrow width effects,location-dependent weighting function, | en |
| dc.relation.page | 45 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2007-07-25 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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