小面積H.264編碼器之設計與實作

Abstract

H.264/AVC 是最新的視訊壓縮標準之ㄧ。這個標準是由ITU-T與ISO/IEC兩個組織共同制定。由於它採用了許多不同以往的技術如支援不同區塊大小之移動評估與可適性亂度編碼技術等，因而使得壓縮效能得以再次提升，並且被廣泛的運用。然而，也由於其採用之技術運算複雜度過高，就算是在很低的需求下也幾乎不可能單純用軟體實現。 本論文中實現一小面積H.264編碼器，其中包含了大部分需要複雜運算的單元。其中各架構之選用與設計均以面積為考量，並經過整合後而可完成H.264之編碼過程。最後，利用TSMC 0.18微米1P6M的製程完成晶片原型之設計，並送交系統晶片中心進行原型的實作。此原型在佈局後可操作於108MHz，其晶片大小約為2.9mm x 2.9mm。

H.264/AVC is one of the latest international video coding standards. This standard is developed by the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. It can achieve higher coding efficiency than previous standards. With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding (AVC) are increasing. However, AVC requires a much higher computation complexity due to the use of coding tools such as variable block sizes motion estimation (VBSME). This makes the pure software solution nearly impossible to work even under low requirement. In this Thesis, we design and implement an area aware H.264 encoder architecture including full search motion estimation, intra prediction, forward and inverse transforms, and forward and inverse quantizations. Many works were done with the consideration of saving area, such as the choice of architectures and the schedule of processes. After combining all these modules, the system can encoder a QCIF picture in 7.13K clocks. After carefully checking the correctness of design, the prototype of the proposed design was implemented in TSMC 0.18μm 1P6M process technology and fabricated by CIC. The maximum operation frequency of the system is 108MHz. The core size of the chip is 2mm x 2mm with a total gate count about 410K and the die size is 2.95mm x 2.95mm after placement and routing.