請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/28707完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳瑞北 | |
| dc.contributor.author | Hsin-Hung Lu | en |
| dc.contributor.author | 呂信宏 | zh_TW |
| dc.date.accessioned | 2021-06-13T00:18:38Z | - |
| dc.date.available | 2011-08-10 | |
| dc.date.copyright | 2011-08-10 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-08-05 | |
| dc.identifier.citation | [1] T. Kushta, K. Narita, T. Kaneko, T. Saeki, and H. Tohya, “Resonance stub effect in a transition from a through via hole to a stripline in multilayer PCBs,” IEEE Trans. Microw. Wireless Compon. Lett., vol. 13, no. 5, pp. 169–171, May 2003.
[2] S. Deng, J. Mao, T. H. Hubing, J. L. Drewniak, J. Fan, J. L. Knighten, N.W. Smith, R. Alexander, and C. Wang, “Effects of open stubs associated with plated through-hole vias in backpanel designs,” in IEEE Int. Symp. Electromagn. Compat., Santa Clara, CA, USA, vol. 3, pp. 1017–1022, Aug. 9-13, 2004. [3] H.-H. Jhuang and T.-W. Huang, “Design for electrical performance of wideband multilayer LTCC microstrip-to-stripline transition,” in Proc. 6th Electron. Packag. Technol. Conf., Singapore, pp. 506–509, Dec. 8-10, 2004. [4] D. Kwon, J. Kim, K. Kim, S. Choi, J. Lim, J.-H. Park, L. Choi, S. Hwang, and S. Lee, “Characterization and modeling of a new via structure in multilayered printed circuit boards” IEEE Trans. Comp. Package. Technol., vol. 26, no.2, pp. 483–489, June 2003. [5] K. Soorya Krishna and M. S. Bhat, “Impedance matching for the reduction of via induced signal reflection in on-chip high speed interconnect lines,” in IEEE Int. Commun. Control Comput. Tech. Conf., Tamilnadu, India, pp. 120–125, Oct. 7-9, 2010. [6] S.-H. Joo, D.-Y. Kim, S.-H. Lee, S.-J. Oh, K.-S. Kang, and H.-Y. Lee, “Resistively-terminated via-stubs for signal integrity improvement in the semiconductor test board,” in Korea-Japan Microw. Conf., Okinawa, Japan, pp 121–124, Nov. 15-16, 2007. [7] E. Song, J. Kim, and J. Kim, “A compact, low-cost, and wide-band passive equalizer design using multi-layer PCB parasitics,” in IEEE 19th Conf. Electr. Perform. Electron. Packag. Syst., Austin, TX, USA, pp 165–168, Oct. 25-27, 2010. [8] S. Han, J. Kim, and D. P. Neikirk, “Impact of pad de-embedding on the extraction of interconnect parameters,” in IEEE Int. Conf. Microelectron. Test Struct. Conf., Austin, TX, USA , pp 76–81, March 6-9, 2006. [9] K.-H. Nam, E.-K. Koh, E.-J. Hong, S.-H. Park, J.-Y. Lee, I.-G. Kwak, and W. Nah, “Pad shape effects on high frequency signal transfer characteristics,” in Electr. Des. Adv. Packag. Syst. Symp., Seoul, Korea, pp 117–119, Dec. 10-12, 2008. [10] C. Ye, X. Ye, and T. Do-Nguyen, “Improve storage IO performance by using 85Ohm package and motherboard routing,” in IEEE 19th Conf. Electr. Perform. Electron. Packag. Syst., Austin, TX, USA, pp 281–284, Oct. 25-27, 2010. [11] B. Mutnury, F. Paglia, J. Mobley, G.. K. Singh, and R. Bellomio, “QuickPath Interconnect (QPI) design and analysis in high speed servers,” in IEEE 19th Conf. Electr. Perform. Electron. Packag. Syst., Austin, TX, USA, pp 265-268, Oct. 25-27, 2010. [12] 郭維德，印刷電路板級損耗傳輸線之眼圖分析與補償設計，國立台灣大學博士論文，2008年10月。 [13] 錢韋寧，連通柱不連續結構之電器特性與補償設計，國立台灣大學碩士論文，2007年6月。 [14] SATA. [Online]. Available: http://www.serialata.org [15] PCI-SIG. [Online]. Available: http://www.pcisig.com [16] Intel® QuickPath Technology, Intel Corporation.. [Online]. Available: http:// http://www.intel.com/technology/quickpath [17] Caswell, Cas Solution Guide. [18] MATLAB®, MathWorks, Inc. [Online]. Available: http://www.mathworks.com [19] Allstron, Inc. [Online]. Available: http://www.allstron.com/index.htm [20] Agilent Technologies. [Online]. Available: http://www.agilent.com [21] PowerSI, Sigrity, Inc. [Online]. Available: http://www.sigrity.com [22] HFSS Version 11, Ansys, Inc. [Online]. Available: http://www.ansys.com [23] Anritsu, Inc. [Online]. Available: http://www.anritsu.com/en-US/home.aspx [24] Tektronix, Inc. [Online]. Available: http://www.tek.com [25] 美麗基科技股份有限公司, [Online]. Available: http://www.turboard.com.tw [26] 捷寶實業有限公司, [Online]. Available: http://www.jyebao.com.tw/index_cn.php [27] Semi-rigid cable connector, [Online]. Available: http://www.jyebao.com.tw/product-1_cn.php#sma [28] SIwave Version 4, Ansys, Inc. [Online]. Available: http://www.ansys.com [29] Q3D Version 6, Ansys, Inc. [Online]. Available: http://www.ansys.com | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/28707 | - |
| dc.description.abstract | 在工業電腦的多層印刷電路板當中，常見許多不連續結構，例如：連通柱與焊墊。隨著資料傳輸速率達到Gbit/s 以上時，這些不連續結構對於信號完整度的影響就必須要被考慮。
為了改善高速訊號完整度於傳輸通道眼圖的電性表現，本論文在差模連通柱殘段的末端使用電阻與電感組成的等化器，並提出一套完整的設計流程來加以設計。並且利用模擬軟體與量測散射參數，就眼圖結果來驗證此方法的正確性。為了減少反射雜訊，本論文使用在焊墊下開槽洞與在差模連通柱使用膠囊狀清潔環的補償方式，來減少訊號的反射。 | zh_TW |
| dc.description.abstract | There are many discontinuities in the industrial personal computer printed circuit board, such as the via and pad. As the transmission data rate exceeds several Gbit/s, the discontinuities have the serious impact on the signal integrity.
To improve the signal integrity on the eye-diagram performance of high-speed channel interconnection, this thesis used the resistor and inductor attached at the via stubs as an equalizer and proposed a design flow, accordingly. The design flow was verified between the simulation tools, scattering parameters, and eye measurements. To reduce the reflection noise, this thesis used the defected ground under the pad and the differential vias with the capsule-shaped anti-pad. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T00:18:38Z (GMT). No. of bitstreams: 1 ntu-100-R98942008-1.pdf: 4824268 bytes, checksum: e7db8bb663308acb90794715c5d7391b (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | 誌 謝 II
摘 要 III ABSTRACT IV 目錄 V 圖目錄 VII 表目錄 XI 第一章 緒論 1 1-1 研究動機 1 1-2 文獻探討與回顧 2 1-3 章節概要 3 1-4 貢獻 3 第二章 工業電腦介紹 5 2-1 高速I / O規格 5 2-2 網路管理主機線路架構 11 2-3 多主機板刀鋒伺服器線路架構 13 第三章 網路管理主機板高速差模訊號線之訊號完整度分析 16 3-1 網路管理主機板高速差模訊號線結構 17 3-2 網路管理主機板高速差模訊號線模擬 20 3-3 利用差模訊號連通柱殘段之等化器設計 23 3-4 實驗量測結果 33 第四章 多主機板刀鋒伺服器高速差模訊號線之訊號完整度分析 41 4-1 多主機板刀鋒伺服器高速差模訊號線結構 41 4-2 多主機板伺服器高速差模訊號線模擬 43 4-3 實驗量測結果 61 第五章 結論與未來工作 65 參考文獻 66 | |
| dc.language.iso | zh-TW | |
| dc.subject | 焊墊 | zh_TW |
| dc.subject | 等化器 | zh_TW |
| dc.subject | 眼圖 | zh_TW |
| dc.subject | 連通柱殘段 | zh_TW |
| dc.subject | pad | en |
| dc.subject | equalizer | en |
| dc.subject | eye diagram | en |
| dc.subject | via | en |
| dc.title | 工業電腦主機板高速訊號線訊號完整度分析與等化器設計 | zh_TW |
| dc.title | Signal Integrity Analysis and Equalizer Design for High-Speed Interconnects in Industrial Personal Computer Mother Board | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃立廷,駱韋仲,吳宗霖,林建民 | |
| dc.subject.keyword | 等化器,眼圖,連通柱殘段,焊墊, | zh_TW |
| dc.subject.keyword | equalizer,eye diagram,via,pad, | en |
| dc.relation.page | 67 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2011-08-05 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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