使用 FPGA 硬體加速之空間成像模擬

Abstract

這篇論文是在討論如何使用FPGA替空間成像模擬作硬體加速。目前這種模擬系統大至都建構在以軟體為基礎的電腦上，因為如果說使用純硬體去解決的話，將會花費較長的設計時間並且難以除錯。使用硬體最大的優勢就在於它的效率十分良好，在一個晶片裡面我們可以用平行化的方式讓多個處理器去做加速。 這篇論文主要的核心就是我們如何發展一個使用FPGA的空間成像模擬器。為了要做快速的模擬，我們最好在稀疏的點去計算影像強度，避免在一般高密度的網格做計算[1]。我們一開始使用了Hopkins的部份一致性成像方程式 (Hopkins partially coherent imaging equations)，這個分 解又被稱為一致性的加總系統結構 (sum of coherent systems - SOCS)。為了要實現這個分解法 ，我們採用了奇異值分解 (singular value decomposition – SVD)，這在之後會在做詳細的說明。 我們知道， 其實每一個一致性系統就是一個線性平移不變 (linear shift invariant system – LSI) 系統， 所以我們可以應用超位置 (superposition)去計算它的卷積 (convolution)。 這部份使 用的輸入 資料，其實是一個 由像是曼哈頓二元幾何光柵的 矩形組合成的 一個函數，空間 成像的計 算可以更進一步的利用IC光柵模範 (mask pattern) 的結構 做加速。我們使用了 一個以查表 為核 心的技術，去處理對於由矩 形組成的光 柵函數一般卷積， 包含了任意的卷 基核心 (kernel)。對於SOCS裡的 N x N 個卷積 核心，被查詢的表格需要O (N x N) 的空間。在 [1] 這篇文獻中指出， 為了要得到 一個點的強度，我們需要 O (Na x Mr) 的計算，其中 Na是高階近似光 學系統的 最高次方項，Mr 是描述光柵區域的矩形個 數。但是透過 FPGA的平行加 速，這 個計算複雜度可以減少成 O (Mr)。在最先進的 模擬技術中， 我們越來越需 要使 用高階近似的光學系統，我們很清楚的可以看到FPGA 是如何有效率的降 低每一個點的強度計算，特別是FPGA它可以做平行處理，以及使用ROM 來加速運算的特性。 在專案最初的階段，我們用XESS公司所設計XSV-800 的 FPGA板去實現這個模 擬系統。 但是相較於大型以及真實的模擬系統，我們舊版本的FPGA板在硬體資源上就顯得不足。雖然 Xilinx 最新版本的 FPGA – Virtex 5 提供了更好的環境， 但很 遺憾我們實驗室並沒有辦 法取得這些設備。我們決定使用合適的軟體去模擬這個系統，它在效能上和功能性都有很好的結果。我們的FPGA內部是使用Verilog程式碼撰寫，用來控制晶片並實現整個空間成像模擬的設計。

This thesis describes a hardware implementation of aerial image simulation in lithography using an FPGA (Field Programmable Gate Array). Such simulators are presently performed using mainly software-based techniques on dedicated computers, as designing pure hardware solutions can be slower and harder to debug. The advantage of hardware designs is in performance, as one chip could be used to parallelize many processes at the same time. A major contribution of this thesis is the development of an aerial image simulator which is accelerated by FPGA. For fast simulation, it is best to compute intensity of image at sparse points rather than on a regular dense grid [1]. We begin with the decomposition of the Hopkins partially coherent imaging equations, this decomposition is called sum of coherent systems (SOCS) structure. The implementation of this decomposition is done numerically by using singular value decomposition (SVD) which is described in detail. It is shown that each of the coherent system is a linear shift invariant (LSI) system, so the convolution can be used to compute their outputs by applying superposition. The data input used here is a function which is consisting of rectangles as Manhattan geometry mask with just two transmission values, e.g. binary masks, the aerial image calculation can be further sped up by utilizing the structure of IC mask patterns. For general convolution of mask functions, consisting of rectangles, with arbitrary convolution kernels, a lookup technique is used and the process is outlined. The storage size needed for lookup tables is numbers for each convolution kernel in the SOCS. In [1] it was shown that to achieve single point intensity computation needs computation on the order of where is the order of approximation to the optical system and is the number of rectangles in the mask region description, but this computation is decreased efficiently by using FPGA to parallelize this operation to yield a computation on the order of . It is clearly shown how FPGA can be utilized efficiently to reduce the cost of each single point intensity computation, since highly demand of high order of approximation order for optical systems is needed nowadays in such simulators, and also the nature of FPGA with spatial computational style and enhanced inherent operations and blocks inside it. The implementation discussed herein uses the XSV-800 FPGA board designed by XESS Corporation in the first stage of this project to implement a simple system. But for bigger and real aerial image simulators, and lacking of hardware resources in old versions of FPGAs, a latest FPGA chip from Xilinx, Virtex 5, is used for this purpose. Because of unavailability of this kind of FPGA’s board in our lab, we decided to study our system by simulating it by suitable software which gives a good indication of performance and functionality. The FPGA is configured with code designed in Verilog that handles control of the chips involved to implement an aerial image simulator design.