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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 盧信嘉(Hsin-Chia Lu) | |
dc.contributor.author | Yung-Shuen Chang | en |
dc.contributor.author | 張詠舜 | zh_TW |
dc.date.accessioned | 2021-06-13T00:05:09Z | - |
dc.date.available | 2008-07-31 | |
dc.date.copyright | 2007-07-31 | |
dc.date.issued | 2007 | |
dc.date.submitted | 2007-07-27 | |
dc.identifier.citation | [1] Shiu-Ping Chao, Yen-Son Huang, Lap Man Yam, 'A Hierarchical Approach for Layout Versus Circuit Consistency Check,' Design Automation, 1980. 17th Conference, on 269- 276, 23-25 June 1980.
[2] Todd J. Wagner, “Hierarchical layout verification,” Proceedings of the 21st conference on Design automation, p.484-489, June 25-27, 1984. [3] Tamal Mukherjee, Bikram Baidya, “Extraction and LVS for mixed-domain integrated MEMS layouts,” ICCAD '02, pp. 361-366, 2002. [4] R. Kulka, M. Mittweger, P. Uhlig, C. Günther, “LTCC-multilayer ceramic for wireless and sensor applications,” IMST GmbH, http://www.ltcc.de, 2001 [5] Peter Hagn, Andreas Przadka, Volker Gebhardt, Ulrich Bauernschmitt, “Ceramics: The Platform for Duplexers and Frontend-Modules,” IEEE Ultrasonics Symp. Vol. 1, pp.1-10, 8-11 Oct. 2002. [6] http://www.mochima.com/articles/cuj_geometry_article/ cuj_geometry_article.html [7] Haines, Eric, 'Point in Polygon Strategies,' Graphics Gems IV, ed. Paul Heckbert, Academic Press, p. 24-46, 1994. [8] Lap Kun Yeung and Ke-Li Wu, “A Compact second-order LTCC bandpass filter with two finite transmission zeros,” IEEE Trans. Microwave Theory and Tech., vol. MTT-51 No. 2, pp. 337~341, Feb. 2003. [9] Hsin-Chia Lu and Tzu-Wei Chao, “Capacitor and coupled inductor with high process tolerance,” 2006 International Microsystems, Packaging, Assembly Conference Taiwan (IMPACT), Dig. pp.47~50, Oct. 2006. [10] Mark de Berg, Marc van Kreveld, Mark Overmars, Otfried Schwarzkopf, “Computational geometry: Algorithms and Applications Second edition,” Springer-Verlag New York, Inc., Secaucus, NJ, 1997 [11] http://boolean.klaasholwerda.nl/algdoc/top.html [12] W. Meier, “Hierarchical layout verification for submicron designs,” Design Automation Conference, 1990. [13] Antonin Guttman, “R-trees: a dynamic index structure for spatial searching,” Proceedings of the 1984 ACM SIGMOD international conference on Management of data, June 18-21, 1984, Boston, Massachusetts. [14] Timos K. Sellis, Nick Roussopoulos, Christos Faloutsos, “The R+-Tree: A Dynamic Index for Multi-Dimensional Objects,” Proceedings of the 13th International Conference on Very Large Data Bases, p.507-518, September 01-04, 1987. [15] Norbert Beckmann, Hans-Peter Kriegel, Ralf Schneider, Bernhard Seeger, “The R*-tree: an efficient and robust access method for points and rectangles,” Proceedings of the 1990 ACM SIGMOD international conference on Management of data, p.322-331, May 23-26, 1990, Atlantic City, New Jersey, United States. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/28322 | - |
dc.description.abstract | 本篇論文可以分為兩大部分。第一部份是有關於元件的萃取,此部份大量應用計算幾何,利用計算幾何並設計演算法來辨識電路元件。電路元件包含電容、電感、分岔與通道。第二部份為電路網路鏈結生成,此部份為設計一演算法,以期能將在多邊形中的電路資訊快速鏈結。可以經由萃取多邊形的點的資訊和邊的關係而生成子網路鏈結,並經由結合全部的子網路鏈結生成全域網路鏈結。此兩部分為佈局對電路圖檢查(Layout vs. schematic check, LVS)之前段作業。 | zh_TW |
dc.description.abstract | There are two parts in this thesis. The first part is about the component extraction, and this part applies a lot of computation geometry algorithms. We use computational geometry to design an algorithm to recognize components. Circuit components extracted include capacitors, inductors, forks and vias. The second part is about netlist generation. In this part, we designed an algorithm to link up all information of polygon effectively. The sub-netlist can be extracted by extracting the point information and the edge relation of polygons, and generate the full netlist. The two parts are the front-end of layout vs. schematic check (LVS). | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T00:05:09Z (GMT). No. of bitstreams: 1 ntu-96-R94943154-1.pdf: 844781 bytes, checksum: 317214cb926fb61f5418c26c9477f3e4 (MD5) Previous issue date: 2007 | en |
dc.description.tableofcontents | 誌謝................................................i
摘要...............................................ii Abstract..........................................iii Table of Contents..................................iv List of Figures....................................vi Chapter 1 Introduction..............................1 1.1 Motivation and organization.....................1 1.2 Netlist Extraction for digital circuits.........2 1.3 Introduction of LTCC technology.................3 1.3.1 Advantages of LTCC technology.................5 1.3.2 Disadvantages of LTCC technology..............6 1.4 Basic forms of inductors and capacitors.........6 Chapter 2 Components extraction.....................7 2.1 Introduction....................................7 2.2 Define corners..................................8 2.3 Intersection test of segment and segment........9 2.4 Point inside a polygon.........................13 2.5 Kd-Tree........................................14 2.6 Entry type port and exit type port.............15 2.7 Pair double-concave corners....................18 2.8 Inductor Extraction............................20 2.8.1 Parallel coupled inductor extraction.........22 2.8.2 Direction of spiral inductor rotation........23 2.9 Pair single-concave corners....................24 2.10 Shape variation of capacitors and fork........25 2.10.1 One-port capacitor..........................26 2.10.2 Two-port capacitor..........................27 2.10.3 Multi-port capacitor and Stable shape.......29 2.11 Combine capacitors............................30 2.12 Extraction flow...............................34 Chapter 3 Netlist generation.......................36 3.1 Introduction...................................36 3.2 Boolean operation..............................36 3.2.1 Calculate intersections......................37 3.2.2 Split polygon................................39 3.2.3 Perform operation............................40 3.3 Via connection.................................41 3.4 Pair capacitors................................42 3.5 Edge tracing...................................45 3.6 Netlist generation.............................47 3.7 Exception......................................48 Chapter 4 Results..................................49 4.1 Introduction...................................49 4.2 5.25GHz band pass filter.......................49 4.3 3~5GHz band pass filter........................53 4.4 3GHz low pass filter...........................57 4.5 Single band filter.............................60 Chapter 5 Conclusion...............................64 Reference..........................................65 Appendix A.........................................66 | |
dc.language.iso | en | |
dc.title | 在微波多層電路佈局圖中電容與電感的萃取 | zh_TW |
dc.title | The extraction of inductors and capacitors from layout of microwave multi-layer circuits | en |
dc.type | Thesis | |
dc.date.schoolyear | 95-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 江介宏(Jie-Hong Jiang),林祐生(Yo-Shen Lin) | |
dc.subject.keyword | 電容,電感,萃取,佈局對電路圖檢查,計算機幾何, | zh_TW |
dc.subject.keyword | capacitor,inductor,extraction,layout vs. schematic check,LVS,computational geometry, | en |
dc.relation.page | 66 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2007-07-30 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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