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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Jyun-Cheng Lin | en |
| dc.contributor.author | 林俊成 | zh_TW |
| dc.date.accessioned | 2021-06-12T18:20:56Z | - |
| dc.date.available | 2008-08-28 | |
| dc.date.copyright | 2007-08-28 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-08-22 | |
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[2] H.H. Chang, J.W. Lin, C.Y. Yang, and S.I. Liu, “A wide-range delay-locked loop with a fixed latency of one clock cycle,” IEEE J. Solid-State Circuits, vol. 37, pp. 1021-1027, Aug. 2002. [3] C. Kim et al., “Low-Power Small-Area ±7.28ps Jitter 1GHz DLL-based Clock Generator,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2002, pp. 142-143. [4] S. I. Liu, J. H. Lee, and H. W. Tsao, “Low-power clock-deskew buffer for high-speed digital circuits,” IEEE J. Solid-State Circuits, vol. 34, pp. 554–558, Apr. 1999. [5] B. Garlepp et al., “A portable digital DLL for high-speed CMOS interface circuits,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 632–644, May 1999. [6] T. Xanthopoulos, D. W. Bailey, A. K. Gangwar, M. K. Gowan, A. K. Jain, and B. K. Prewitt, “The design and analysis of the clock distribution network for a 1.2 GHz alpha microprocessor,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2001, pp. 402–403. [7] S. Tam et al., “Clock generation and distribution for the first IA-64 microprocessor,” IEEE J. Solid-State Circuits, vol. 35, pp. 1545–1552, Nov. 2000. [8] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996. [9] F. Gardner, “Charge-pump phase-lock loops,” IEEE Tran. Communication, vol. 28, pp. 1849-1858, Nov, 1980. [10] F. Herzel, B. Razavi, “A study of oscillator jitter due to supply and substrate noise,” IEEE Trans. Circuit Syst. II, vol. 46, pp. 56-62, Jan. 1999. [11] M.-J. E. Lee, W. J. Dally, T. Greer, H.-T. Ng, R. Farjad-Rad, J. Poulton, and R. Senthinathan, “Jitter transfer characteristics of delay-locked loops-Theories and design techniques,” IEEE J. Solid-State Circuits, vol. 38, pp. 614-621, Apr. 2003. [12] B.-G. Kim, L.-S. Kim, “A 250MHz-2GHz Wide-Range Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1310-1321, May 2005. [13] S. Kim, K. Lee, Y. Moon, D.-K. Jeong, Y. Choi, and H. K. Lim, “A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 691–700, May 1997. [14] M. G. Johnson and F. L. Hudson, “A Variable Delay Line PLL for CPU-Coprocessor Synchronization,” IEEE J. Solid-State Circuits, vol. 23, pp. 1218-1223, Oct. 1988. [15] Ian A. Young, “A PLL clock generator with 5 to 110 MHz of lock range for microprocessors,” IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp. 1599-1607. Nov. 1992. [16] S. Sidiropoulos and M. A. Horowitz, “A semi-digital dual delay-locked loop,” IEEE J. Solid-State Circuits, vol. 32, pp. 1689-1692, Nov. 1997. [17] G.-K. Dehng, J.-W. Lin, S.-I. Liu, “A Fast-Lock Mixed-Mode DLL Using a 2-b SAR Algorithm,” IEEE J. Solid-State Circuits, vol. 36, pp. 1464-1471, Oct. 2001 [18] A. Hatakeyama, H. Mochizuki, T. Aikawa, M. Takita, Y. Ishii, H.Tsuboi, S. Fujioka, S. Yamaguchi, M. Koga, Y. Serizawa, K. Nishimura,K. Kawabata, Y. Okajima, M.Kawano, H. Kojima, K. Mizutani, T.Anozaki, M. Hasegawa, and M. Taguchi, “A 256 Mb SDRAM using a register-controlled digital DLL,” IEEE J. Solid-State Circuits, vol. 32, pp.1728–1733, Nov. 1997. [19] F. Lin, J. Miller, A. Schoenfeld, M. Ma and R. J. Baker, “A register-controlled synnetrical DLL for double-data-rate DRAM,” IEEE J. Solid-State Circuits, vol. 34, pp. 565-568, Apr. 1999. [20] H. Sutoh, K. Yamakoshi, and M. Ino, “Circuit technique for skew-free clock distribution,” in IEEE Custom Integrated Circuits Conf., 1995, pp.163–166. [21] T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, K. Nagata, K. Sakakibara, T. Matano, Y. Hoshino, K. Miyano, S. Isa, S. Nakazawa, E. Kakehashi, J. M. Drynan, M. Komuro, T. Fukase, H. Iwasaki, M. Takenaka, J. Sekine, M. Igeta, N. Nakanishi, T. Itani, K. Yoshida, H. Yoshino, S. Hashimoto, T. Yoshii, M. Ichinose, T. Imura, M. Uziie, S. Kikuchi, K. Koyama, Y. Fukuzo, and T. Okuda, “A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay,” IEEE J. Solid-State Circuits, vol. 31, pp. 1656–1668, Nov. 1996. [22] G. K. Dehng, J. M. Hsu, C. Y. Yang, and S. I. Liu, “Clock-deskew buffer using a SAR-controlled delay-locked loop,” IEEE J. Solid-State Circuits, vol. 35, pp. 1128–1136, Aug. 2000 [23] U. Tietze and Ch. Schenk, Electronic Circuits―Design And applications. New York, NY: Spring-Verlag, 1992, p. 703. [24] A. Rossi and G. Fucilli, “Nonredundant successive approximation register for A/D converters,” Electron. Lett., vol. 32, no. 12, pp. 1055-1057, June 1996. [25] J. J. Kim, S. B. Lee, T. S. Jung, C. H. Kim, S. I. Cho, and B. Kim, “A low-jitter mixed-mode DLL for high-speed DRAM applications,” IEEE J. Solid-State Circuits, vol. 35, pp. 1430–1436, Oct. 2000. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/27794 | - |
| dc.description.abstract | 在傳統的連續逼近式延遲鎖相迴路中，由於響應時間的關係，鎖定時間仍然大大地增加，為了改善鎖定速度，本論文提出一個數位延遲鎖相迴路，可以達到低功率且快速鎖定的特性。本晶片使用台積電0.13-μm 1P8M CMOS 製程製作，晶片面積為0.77 x 0.79mm2，核心面積為0.226 x 0.076mm2，操作頻率範圍從50MHz到200MHz，在最高操作頻率下，量測到的功率消耗為0.259mW，鎖定時間為4個時脈週期，當操作頻率為200MHz的時候，量測到的方均根抖動和峰值抖動分別是3.67ps和34.17ps。 | zh_TW |
| dc.description.abstract | In conventional SARDLL, the lock time still increases seriously because of the response time. A digital DLL is proposed in this work to improve the locking speed. The proposed DLL can exhibit features of low-power and fast-lock. This work is fabricated in TSMC 0.13-μm 1P8M CMOS technology. The chip area is 0.77 x 0.79mm2, and the active area is 0.226 x 0.076mm2. The proposed DLL can operate in the range from 50MHz to 200MHz. The measured power consumption is 0.259mW at the maximum operation frequency 200MHz. The lock time is 4 clock cycles. When the operation frequency is 200MHz, the measured rms jitter and peak-to-peak jitter is 3.67ps and 34.17ps, respectively. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-12T18:20:56Z (GMT). No. of bitstreams: 1 ntu-96-R94943103-1.pdf: 5926960 bytes, checksum: dfd6a07286afd39a6361437952d7e159 (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | Table of Contents
摘要 I Abstract II Table of Contents III List of Figures V List of Tables VII Chapter 1 The Basic Theory of the Delay-Locked Loops......1 1.1 Introduction 1 1.2 The review of the delay-locked loop 2 1.3 The stability and the model of the DLL 4 1.3.1 Charge pump DLL model 4 1.3.2 Stability analysis 5 1.4 Jitter analysis 6 1.4.1 Jitter definition 6 1.4.2 Jitter transfer function 8 1.4.3 Jitter peaking 9 1.5 The building blocks of DLLs 10 1.5.1 Phase detector 10 1.5.2 Charge pump 12 1.5.3 Voltage-controlled delay line 16 Chapter 2 Review of Digital DLL Architectures.............19 2.1 Introduction 19 2.2 Digital DLL architectures 21 2.2.1 Register-controlled DLL 21 2.2.2 Counter-controlled DLL 22 2.2.3 SAR-controlled DLL 24 2.3 Proposed digital DLL 27 Chapter 3 A low-power fast-lock digital DLL..............28 3.1 Searching Algorithm 28 3.2 Architecture 29 3.3 Circuit Implement 32 3.3.1 Encoder 32 3.3.2 Half Delay 36 3.3.3 Delay Cell 37 3.3.4 Multiplexer 38 3.4 Simulation Results 39 Chapter 4 Test Setup and Measurement Results..............47 4.1 Test Setup 47 4.2 Print Circuit Board Layout 48 4.3 Experiment Results 51 4.4 Summary 57 Chapter 5 Conclusion and Future works.....................60 5.1 Conclusions 60 5.2 Future works 60 Bibliography..............................................62 | |
| dc.language.iso | en | |
| dc.subject | 延遲鎖相迴路 | zh_TW |
| dc.subject | 鎖定時間 | zh_TW |
| dc.subject | DLL | en |
| dc.subject | lock time | en |
| dc.title | 一個低功率且快速鎖定的數位延遲鎖相迴路 | zh_TW |
| dc.title | A low-power fast-lock digital Delay-Locked Loop | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢,陳怡然,洪士灝 | |
| dc.subject.keyword | 延遲鎖相迴路,鎖定時間, | zh_TW |
| dc.subject.keyword | DLL,lock time, | en |
| dc.relation.page | 64 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2007-08-23 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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