採用改良型全速率二元式相位偵測器之時脈資料回復電路

Abstract

資料時脈回復電路有線通訊系統中扮演一個重要的角色，因為傳輸的資料經過通道(光纖，傳輸線…)時，會因為通道品質的因素使得資料特性惡化及產生不同步現象，造成接收機後部電路無法得到正確的資料，所以使用資料時脈回復電路來將資料與時脈回復到較佳的狀態，得以讓後部電路得到正確的資料加以處理。隨著時代進步，對速度的要求也愈來愈快，所以因應不同的規格，速度由幾百Mbps到數十Gbps都有，架構從處理單一頻帶到連續性頻帶皆有。 此論文是應用於Video Electronics Standards Association(VESA)所提出的一個新的視訊傳輸介面DisplayPort。此傳輸介面會依通道品質而使用高速率2.7Gbps或低速率1.62Gbps的傳輸速率。因為此規格需要處理兩個頻率，所以我們需要一個雙頻帶的資料及時脈回復電路。此論文使用一個具有大範圍頻率調整與低KVCO的雙控制壓控振盪器來涵蓋所需頻率，以及提出一個創新的二元式相位偵測器，此相位偵測器使用的面積小，具有自我回復資料，三狀態輸出與低抖動輸出，所以此論文使用了一個能兼具大範圍頻率鎖定的架構及降低抖動範圍的相位偵測器，此時脈資料回復電路大約消耗65毫瓦的功率，其主動元件的面積約為 mm2。在輸入1.62Gps 27-1的PRBS的資料下，量測的時脈峰對峰抖動與方均根抖動分別為155.11微微秒與22.87微微秒。在輸入2.7Gps 27-1的PRBS的資料下，量測的時脈峰對峰抖動與方均根抖動分別為101.13微微秒與14.06微微秒。

A clock and data recovery (CDR) circuit plays an important role in wired communication systems. Due to the quality of the channel, the data received at the receiver end is asynchronous and noisy, so a CDR circuit is needed to extract a clean clock from the received data to allow succeeding synchronous operation and sample the center point of the received data to retime data. Progress with era, the demand of the high speed communication (such as SONET, Fiber channel, and Gigabit Ethernet, etc.) and high quality media (such as PCI Express, HDMI, and DisplayPort [1], etc.) is rising. Thus CDR is required to own different operating speeds or different architectures to support different specifications. The operating speed is from several MHz to several GHz and the architectures are the single rate, the multi-rate, or the continuous-rate. This circuit is designed to support data rates of 1.62 and 2.7Gbps without reference clock for ANSI8B/10B format. In this chapter, a modified dual-controlled voltage controlled oscillator (VCO) and a full-rate bang-bang phase detector (BBPD) and are presented for a dual-band bang-bang CDR circuit. The modified dual-controlled VCO is presented to enlarge the tuning range and reduce the VCO gain (KVCO). The proposed BBPD needs fewer devices and produces lower jitter than Alexander BBPD. Moreover, it does not need extra decision circuit to retime data and doesn’t have long run problems. This CDR is fabricated in TSMC 0.18- m CMOS technology with an area of . The power dissipation without the output buffer is 65 mW under a 1.8V supply. When the CDR circuit receives 1.62Gbps 27-1 PRBS data, the measured clock’s rms and peak-to-peak jitter are 23.87ps and 155.11ps respectively. When it receives 2.7Gbps 27-1 PRBS data, the measured clock’s rms and peak-to-peak jitter are 14.06ps and 101.13ps respectively.