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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/27309完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李致毅(Jri Lee) | |
| dc.contributor.author | Yen-Lin Huang | en |
| dc.contributor.author | 黃彥霖 | zh_TW |
| dc.date.accessioned | 2021-06-12T18:00:49Z | - |
| dc.date.available | 2011-01-30 | |
| dc.date.copyright | 2008-01-30 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-01-26 | |
| dc.identifier.citation | Biography
[1] IEEE 802.15 WPAN Millimeter Wave Alternative PHY Task Group 3c (TG3c); http://www.ieeee802.org/15/pub/TG3c.html [2] L. Yujiri, M. Shoucri, P. Moffa, “Passvie mm-Wave Imaging,” IEEE Microwave Magazine,vol. 4, issue 3, pp. 39-50, Sept. 2003. [3] S. Reynolds et al., “60GHz Transceiver Circuits in SiGe Bipolar Technology,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. of Tech. Papers, pp. 442–443, Feb. 2004. [4] B. Razavi, “A 60-GHz CMOS Receiver Front End,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 17-22, Jan. 2006. [5] C. H. Doan et al, “A 60-GHz Downconverting CMOS Single-Gate Mixer,” RFIC Dig. of Tech. Paper, pp. 163-166, June 2005. [6] D. Huang et al, “A 60 GHz CMOS VCO Using On-Chip Resonator with Embedded Artificial Dielectric for Size, Loss, and Noise Reduction,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. of Tech. Papers, pp. 314-315, Feb. 2006. [7] K. Yamamoto and M. Fujishima, “70-GHz CMOS Harmonic Injection-Locked Divider,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. of Tech. Papers, pp. 600–601, Feb. 2006. [8] T. Yao et al, “60-GHz PA and LNA in 90-nm RF CMOS,” RFIC Dig. of Tech. Paper, pp. 147-150, June 2006. [9] H. T. Friis, “Noise Figure of Radio Receivers,” Proc. IRE, vol. 32, pp. 419-422, July 1944. [10] Behzad Razavi, “RF Microelectronics,” Prentice Hall Inc., 1998 [11] L. W. Couch, “Digital and Analog Communication Systems,” 4th ed., New York: Macmillan, 1993. [12] Fuqin Xiong, “Digital Modulation Techniques,” Boston: Artech House, 2000. [13] A. A. Abidi, “Direct-Conversion Radio Transceivers for Digital Communications,” IEEE Journal of Solid-State Circuits, vol. 30, pp. 1399-1410, June 1997. [14] T. Yao et al, “Algorithmic Design of CMOS LNAs and Pas for 60-GHz Radio,” IEEE Journal of Solid-State Circuits, vol. 42, pp. 1044-1057, May 2007. [15] S. A. Sanielevici et al, “A 900-MHz transceiver chipset for two-way paging applications,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 2160-2168, Dec. 1998. [16] T. O. Dickson et al, “The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 1830-1845, Aug. 2006. [17] H. Darabi and A. A. Abidi, “Noise in RF-CMOS mixers: A simple physical model,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 15-25, Jan. 2000. [18] B. De Muer and M. Steyaert, “A 12 GHz/128 frequency divider in 0.250.25μm CMOS,” ESSCIRC’00, pp. 248–251, Sept. 2000. [19] B. Razavi et al., “A 13.4-GHz CMOS Frequency Divider,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. of Tech. Papers, pp. 176–177, Feb. 1994. [20] HongMo Wang, “A 1.8V 3mW 16.8GHz Frequency Divider in 0.25μm CMOS,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. of Tech. Papers, pp. 196–197,Feb. 2000. [21] H. Wohlmuth et al., “A High Sensitivity Static 2:1 Frequency Divider up to 27GHz in 120nm CMOS,” ESSCIRC’02, pp. 24–26, Sept. 2002. [22] Mina Danesh and John R. Long, “Differentially Driven Symmetric Microstrip Inductors,” IEEE Journal of Solid-State Circuits, vol. 50, pp. 332-341, Jan. 2000. [23] S. Reynolds et al., “A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 2820-2831, Dec. 2006. [24] B. Razavi, “A mm-Wave CMOS Heterodyne Receiver with On-Chip LO and Divider,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. of Tech. Papers, pp. 188–189, Feb. 2007. [25] S. Emami et al., “A Highly-Integrated 60-GHz CMOS Front-End Receiver,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. of Tech. Papers, pp. 190–191, Feb. 2007. [26] Toshiya Mitomo et al., “A 60-GHz CMOS Receiver with Frequency Synthesizer,” Symposium on VLSI circuits Dig. of Tech. Papers, pp. 190–191, Feb. 2007. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/27309 | - |
| dc.description.abstract | 我們提出一個採用兩次降頻的外差式接收機，它可減緩振盪器及除頻器的速度需求。此接收機包含低雜訊放大器，射頻混波器，中頻放大器，兩組中頻混波器和正交相位除頻器。此正交相位除頻器可產生正交相位之本地端振盪訊號，使接收訊號達成正交分離的效果。此外差式接收機採用九十奈米互補式金氧半場效電晶體製程製作，其操作在54.7至58.3 GHz時，可達到7.3至9.1 dB之雜訊指數和21.8至24.8 dB之電壓轉換增益。射頻訊號經由接收機降頻後之正交訊號，其增益誤差小於1.6 dB，角度誤差小於1.1度。此接收機電路在1.5 V電壓操作下消耗75 mW | zh_TW |
| dc.description.abstract | A heterodyne receiver performs frequency down conversion in two steps to relax oscillator and divider speed requirements. This receiver incorporates a low noise amplifier, a RF mixer, a IF amplifier, two sets of IF mixers and a injection-locked quadrature frequency divider to generate LO signals for I/Q separation. Fabricated in 90-nm digital CMOS technology, the receiver achieves a noise figure of 7.3 to 9.1 dB from 54.7 to 58.3 GHz with a conversion gain of 21.8 to 24.8 dB and I/Q mismatch of 1.6dB/1.1 degrees. The circuit consumes 75 mW from a 1.5-V supply. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-12T18:00:49Z (GMT). No. of bitstreams: 1 ntu-97-R94943034-1.pdf: 4144469 bytes, checksum: 939236972f7e975f2cd9bb6db44837fa (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | Contents
口試委員會審定書 iii 摘要 vii Abstract ix Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivation 3 1.3 Thesis Organization 4 Chapter 2 Fundamental of Wireless Receiver 5 2.1 Nonlinearity 5 2.2 Noise Figure 9 2.3 Sensitivity and Dynamic Range 11 2.4 Digital Modulation 13 2.4.1 Basic Concept 13 2.4.2 Binary Modulation 15 2.4.3 Quadrature Modulation 22 2.5 Various Receiver Architectures 29 2.5.1 Heterodyne Receivers 29 2.5.2 Homodyne Receivers 30 2.5.3 Low-IF Receivers 33 Chapter 3 Design of 60-GHz Heterodyne Receiver 35 3.1 Millimeter-wave Design Challenges 35 3.2 Receiver Architecture 37 3.3 Building Blocks 38 3.3.1 Low-Noise Amplifier 38 3.3.2 Mixers 44 3.3.3 Quadrature Frequency Divider 52 Chapter 4 Measurement Result 55 4.1 Layout and Testing Setup 55 4.2 Measurement Result of 60-GHz Heterodyne Receiver 59 Chapter 5 Conclusion 65 Biography 66 | |
| dc.language.iso | en | |
| dc.title | 應用於60-GHz無線通訊系統之外差式接收機 | zh_TW |
| dc.title | A Heterodyne Receiver for 60-GHz Wireless Communication Systems | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),盧信嘉(Hsin-Chia Lu) | |
| dc.subject.keyword | 60-GHz,外差式接收機,注入鎖定正交相位除頻器, | zh_TW |
| dc.subject.keyword | 60-GHz,Heterodyne receiver,Injection-locked quadrature frequency divider, | en |
| dc.relation.page | 68 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-01-28 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-97-1.pdf 目前未授權公開取用 | 4.05 MB | Adobe PDF |
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