請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/27270完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 曹恆偉 | |
| dc.contributor.author | Tse-Yi Wu | en |
| dc.contributor.author | 吳則毅 | zh_TW |
| dc.date.accessioned | 2021-06-12T17:59:41Z | - |
| dc.date.available | 2008-02-01 | |
| dc.date.copyright | 2008-02-01 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-01-28 | |
| dc.identifier.citation | 1. Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10Gb/s Operation. IEEE std, 802.3ae, 2002.
2. B. Razavi, “Design of Integrated Circuits for Optical Communication, McGRAW -Hill, 2003. 3. J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IIEEE J, Solid-State Circuits, vol.31, pp. 1723-1732, Nov. 1996. 4. C. Hogge, “A self-correcting clock recovery circuit,” IEEE J. Lightwave Technology, vol. LT-3, no. 6, pp. 1312-1314, Dec,1985. 5. F. Herzel and B.Razavi, “A Study of Oscillator Jitter Due to Supply and Substrate Noise,“ IEEE Trans. Circuit and Systems, Part II, vol. 46, pp. 56-62, Jan. 1999. 6. R. Kreienkamp, U. Langmann, C.Zimmermann, T. Aoyama, and H. Siedhoff, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with an analog phase interpolator,” IEEE J. solid-state circuit, vol. 40, pp. 736-743, March 2005. 7. http://users.rcn.com/wpacino/jitwtutr/jitwtutr.htm 8. J. Savoj and B. Razavi, “A 10Gb/s CMOS clock and data recovery circuit,” in Sump. VLSI Circuits Dig. Tech. Papers, pp. 136-139, Jun. 2000. 9. J. Savoj and B. Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-rate Linear Phase Detector,” IEEE J. solid-state Circuit, vol.36, pp. 761-768, May 2001. 10. A. Tanabe and M. Umetani, “0.18um CMOS 10-Gb/s Multrplexer / Demultiplexer ICs Using Current Mode Logic with Tolerance to Threshold Voltage Fluctuation,” IEEE J. Solid-state Circuits, June 2001. 11. Y. Moon, D.K. Jeong, and G. Ahn, ”A 0.6-2.5GBaud CMOS tracked 3X oversampling transceiver with dead-zone phase detection for robust clock/data recovery” ISSCC Digest of Technical papers, pp. 212-213, Feb 2001. 12. Yan and Luong, “A 900-MHz CMOS low-phase-noise voltage control oscillator” IEEE Transactions on circuits and systems ,vol.48 ,no. 1 , January 2001. 13. J. Lee and B. Kim, “A low noise fast lock phase-locked loop with adaptive bandwidth control”, IEEE J. solid-state circuit, vol.35, pp.1137-1145, Aug. 2000. 14. B. stilling, “Bit rate and protocol independent clock and data recovery” Electronics letters, vol.36, pp.824-825, Ari. 2000. 15. 劉深淵,楊清淵, “鎖相迴路”滄海書局, 2006. 16. G. Gutierrez and S Kong, ”Unaided 2.5 Gb/s Silicon Bipolar clock and data recovery IC,” IEEE Radio Freq. int. Circuits Sump. , 1998. 17. X. Maillard, F. Devisch, and M. Kuijk, “A 900-Mb/s CMOS Data Recovery DLL using half-frequency clock” IEEE J. solid-state circuit, vol.37, pp.711-715, June 2002. 18. 凃維軒, ”10Gbase-LX4 ethernet clock and data recovery circuit design” 國立台灣大學電子工程學研究所碩士論文2003 19. 謝宜政, ”Design and implementation of a clock and data recovery circuit for 10Gbase-LX4” 國立台灣大學電子工程學研究所碩士論文2005 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/27270 | - |
| dc.description.abstract | 隨著網際網路的快速發展與普及，人們對於網路通信頻寬的需求急遽成長，區域網路的頻寬也已在近幾年內跨入百億位元乙太網路的新紀元。在國際電子暨電機工程師協會所制定的百億位元乙太網路規格中，10GBase-LX4 使用低成本的雷射二極體，光二極體及多模或單模光纖作為光通訊的媒介，相信10GBase-LX4 的規格將會在下一代乙太網路中扮演主要角色。
10GBase-LX4 這個規格是一個使用多路接收機（3.125G*4）的應用，這樣的系統不建議使用傳統的鎖相迴路資料回復電路，因為LC壓控振盪器之間會透過基底或是電磁場產生交互影響，所以本論文提出一個讓多路資料回復電路使用同一個振盪器產生之時脈的架構，且能具有低功率及小面積的特性。整個晶片的實現是使用台積電0.18μm 1P6M CMOS 製程，所佔面積為0.8mm * 0.68mm 。在1.8伏特的電壓下總消耗功率為80mW。 | zh_TW |
| dc.description.abstract | With the fast proliferation and development of the Internet, the demand for high-speed communication networks has grown progressively. The bandwidth of local area network (LAN) has also already entered the new era of the 10 Gigabit Ethernet in recent years. By IEEE standard of the 10 Gigabit Ethernet, 10GBase-LX4 specification utilizes low-cost laser diodes, optical diodes, and multi-mode or single-mode fibers. It is believed that 10GBase-LX4 will play an important role in the Ethernet in the near future.
10GBase-LX4 specification is an application of multi-channel receiver (3.125G*4), which is a system not suitable for traditional PLL-based CDR due to the mutual effects of LC-tank VCO caused by the substrate or the electromagnetic field. Therefore, this thesis proposed a architecture for multi-channel CDR to use the clocks generated from the same VCO—a architecture that is not only power-efficient but also space-saving. This 0.8mm x 0.68mm chip is applied to the producing process of TSMC 0.18μm 1P6M CMOS. Its total power consumption is 80mW under the voltage of 1.8 volts. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-12T17:59:41Z (GMT). No. of bitstreams: 1 ntu-97-R92943083-1.pdf: 9558529 bytes, checksum: 99cd5033699f5811a063f543c0e73b54 (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 摘要 I
Abstract II 目錄 III 表目錄 VI 圖目錄 VII 第一章 1 1.1 動機 1 1.2 系統簡介 1 1.3 規格簡介 2 1.4 論文組織 4 第二章 5 2.1 時脈資料回復電路的架構 5 2.1.1 全速率與半速率時脈資料回復電路 6 2.1.2 無本地參考時脈的時脈資料回復電路 7 2.1.3 有本地參考時脈的時脈資料回復電路 8 2.2 時脈資料回復電路的組成單元 10 2.2.1 相位偵測器 10 2.2.2 頻率偵測器 13 2.2.3 壓控振盪器 15 2.3 系統參數設計 17 2.3.1 鎖相迴路的線性模型 17 2.3.2 輸入端的雜訊分析 18 2.3.3 壓控振盪器的雜訊分析 18 2.4 抖動分析 19 2.4.1 抖動產生 20 2.4.2 抖動轉移 21 2.4.3 抖動容忍度 22 第三章 24 3.1 多路時脈資料回復電路 24 3.2 參數設計 28 3.2.1 鎖相迴路(迴路2) 28 3.2.2 延遲鎖定迴路(迴路3) 35 3.3 電路組成單元 36 3.3.1 半速率相位偵測器與電壓電流轉換器 36 3.3.2 雙控制壓控振盪器與壓控延遲線 43 3.3.3 自我校正電路[17] 51 3.3.4 頻率偵測器[14]與電荷幫浦[15] 53 3.3.5 除頻器 55 3.3.6 鎖定偵測器[16] 57 3.4 閉迴路模擬結果 58 3.5 佈局平面圖及佈局後模擬結果 59 3.5.1 佈局平面圖 59 3.5.2 佈局後模擬結果 60 3.5.3 相關作品比較 61 第四章 62 4.1 量測考量 62 4.2 量測環境 63 4.3 印刷電路板設計 63 4.4 電路量測結果與分析 65 4.4.1 振盪器量測 65 4.4.2 時脈資料回復電路量測 66 4.5 電路改進方式 69 第五章 70 參考書目 71 | |
| dc.language.iso | zh-TW | |
| dc.title | 用於百億位元乙太網路(LX4)之多路時脈與資料回復電路 | zh_TW |
| dc.title | Multi-Channel Clock and Data Recovery Circuit for 10GBASE-LX4 Ethernet | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢,李泰成,陳伯奇 | |
| dc.subject.keyword | 時脈資料回復電路,半速率,雙輸入壓控振盪器,多路時脈資料回復電路,百億位元乙太網路(LX4), | zh_TW |
| dc.subject.keyword | Clock and Data Recovery circuit,half-rate,dual-control VCO,Multi-channel CDR,10GBASE_LX4, | en |
| dc.relation.page | 72 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-01-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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