微波多層電路之佈局對電路檢查的後段： 電路之比對

Abstract

本篇論文主要是探討實體驗證中佈局與線路比對檢測，分為三大部分。第一部份是有關將dsn電路檔讀出的netlist文字檔轉換成易於了解的圖形連線方式。第二部份為判斷電路的各個接口間DC是否有流通。第三部份為處理比對電路示意圖和佈局的網路連接方式，並經由比對後的結果驗證佈局的結果。此三部分為LVS之後段作業。

This thesis is focus on the back-end of layout vs. schematic check. It is divided into three parts. The first part is to convert shematic dsn file into a graphic representation. The second part is to check the DC path between any circuit ports. The third part is the schematic mapping between user supplied schematic and schematic extracted from layout of microwave multi-layer circuits. This can help designer to validate his/her layout. These three parts forms the back-end of layout vs. schematic (LVS) check.