嵌入式矽智財核心之IEEE 1500安全測試封套

Abstract

本論文提出一個可防止掃描測試攻擊之安全測試封套，此技術使用安全機制來保護核心電路之主要輸入端與內部掃描鏈輸出入端。此安全架構只允許授權者執行所有測試運作，並需透過安全控制器來驗證測試圖樣是否相同於測試封套密鑰。而測試封套密鑰是由安全封套周邊單元所構成之線性回授位移暫存器(LFSR)所產生。另外此架構對於AES電路將增加約5%之面積成本，但可提供之高安全複雜度(2256)。在系統晶片內此安全架構將維持IEEE 1500標準測試封套之特性，且不需要更動系統晶片內嵌之核心電路。本論文實作安全測試封套之編譯與驗證之自動化軟體，其提升包覆測試封套核心電路之安全性，並可生成測試樣板來驗證安全測試封套之功能及核心電路。另外也實作一個使用者介面平台，整合安全測試封套與IEEE 1500標準測試封套之編譯與驗證軟體，提供指令模式之設計流程來輔助設計者設計與驗證封套架構。

This thesis presents a new secure test wrapper (STW) design for preventing scan-based attack. The technique provides a secure mechanism to protect primary inputs and scan in/out of internal scan chains in IP core. The secure architecture allows only authorized user to execute all test operation by using secure controller to verify whether test pattern is identical to test wrapper key. The test wrapper key is generated by linear-feedback shift register (LFSR) that is constructed from secure wrapper boundary cell. Experimental results on AES show that STW provides very high security (2256) for a small area overhead (approximately 5%). The architecture is compatible to IEEE 1500 standard and there is no need to modify the embedded IP core in System on Chip (SOC). An automatic compiler and validation tool for secure test wrapper is implemented. The user interface platform that includes compiler and validation tool of secure test wrapper and standard test wrapper is also implemented.