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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 賴飛羆 | |
dc.contributor.author | Yu-Chu Tsai | en |
dc.contributor.author | 蔡育筑 | zh_TW |
dc.date.accessioned | 2021-06-08T07:31:05Z | - |
dc.date.copyright | 2008-07-02 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-06-25 | |
dc.identifier.citation | References
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Hara. “A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies.” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1601 – 1609, Nov. 1996. [16] R. Foss, and A. Roth, “Priority encoder circuit and method for content addressable memory,” Canadian Patent 2365891, Apr. 30, 2003. [17] W. Fung, “Low power circuits for multiple match resolution and detection in ternary CAM,” MASc thesis, Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada, 2004. [18] T. Jamil, “RAM versus CAM,” IEEE Potentials, vol. 16, pp. 26-29, Apr.-May, 1997. [19] S. V. Kartalopoulos, “An associative RAM-based CAM and its application to broad-band communications systems,” IEEE Trans. Neural Networks, vol. 9, pp. 1036-1041, Sep. 1998. [20] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE, 91(2):305–327, 2003. [21] Z. Chen, M. Johnson, L. Wei, and K. Roy. Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. ACM/IEEE International Symposium on Low Power Electronics and Design, pages 239–244, 1998. [22] N. Azizi Challenges in Nanometre ” Digital Integrated Circuit Design” 2007 [23] K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) Circuits and architectures: a tutorial and survey,” IEEE J. Solid-State Circuits, vol. 41, pp.712-727, Mar. 2006. [24] H. Miyatake, M. Tanaka, and Y. Mori, “A design for high-speed low-power CMOS fully parallel content-addressable memory macros,” IEEE J. Solid-State Circuits, vol. 36, pp. 956-968, June 2001. [25] C. A. Zukowski and S. Y. Wang, “Use of selective precharge for low-power content-addressable memories,” in Proc. IEEE Int. Symp. Circuits Syst., June 1997, vol. 3, pp. 1788-1791. [26] G. Thirugnanam, N. Vijaykrishnan, and M. J. Irwin, “A novel low power CAM designs,” in Proc. IEEE Int. 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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26895 | - |
dc.description.abstract | 對一個內容可定址記憶體的電路設計者言,大部分所面臨的挑戰是過高的功率消耗,本論文設計一個256行 × 144位元的內容可定址記憶體,主要是使用正回授定址線的方法來減少內容可定址記憶體的功率消耗。利用減少定址線動作時所耗的功率,相較於傳統的內容可定址記憶體電路設計,不但可以避免動態電路的諸多缺點,更可降低整個電路的功率消耗及增加比對速度。我們在0.18 μm 製程及1.8 V 的情況下,由模擬結果顯示出使用所提出的正回授定址線方法可達到0.9 ns的搜尋時間,與傳統NOR形式定址線的架構相比,在功率與延遲時間的乘積上可減少高達63%。最後,我們提出內容可定址記憶體完整的電路設計與分析, 並且與其他的電路設計做比較。 | zh_TW |
dc.description.abstract | Content addressable memories (CAMs) are hardware-based parallel lookup tables with
bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network routers. Despite the attractive features of CAMs, high power consumption is one of the most critical challenges faced by CAM designers, This work proposes circuit techniques for reducing CAM power consumption. The main contribution of this work is reduction in match line (ML) sensing energy, and static-power reduction techniques. The ML sensing energy is reduced by employing positive-feedback ML sense amplifiers (MLSAs). We simulate the circuit with TSMC 0.18 μm process at 1.8 V. The simulation results of the postive-feedback MLSA show 86.3% reduction in ML power-delay product. Finally, design and analysis of a complete CAM circuit are presented, and compared with other published designs. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T07:31:05Z (GMT). No. of bitstreams: 1 ntu-97-J95921054-1.pdf: 1436015 bytes, checksum: c001e13326f9f6860207ef46415e0ae9 (MD5) Previous issue date: 2008 | en |
dc.description.tableofcontents | Chapter 1 ...........................................................................................................................................1
Introduction...............................................................................................................................1 1.1 Applications of CAM .....................................................................................................2 1.2 Comparison between RAM and CAM.........................................................................3 1.3 Research Motivation......................................................................................................4 1.4 Organization of the Thesis ............................................................................................5 Chapter 2 ...........................................................................................................................................6 Background ...............................................................................................................................6 2.1 Leakage Currents..............................................................................................................6 2.1.1 Subthreshold Leakage ...........................................................................................7 2.1.2 Gate Leakage..........................................................................................................9 2.2 Process Variations .............................................................................................................9 2.2.1 Parameter Variations ............................................................................................9 2.2.1.1 Channel Length…………………………………………………………...9 2.2.1.2 Threshold Voltage……………………………………………………….10 Chapter 3 .........................................................................................................................................12 CAM Circuits and Architecture .............................................................................................12 3.1 CAM Architecture ..........................................................................................................12 3.2 CAM Cells........................................................................................................................15 3.2.1 Cell Basics .............................................................................................................16 3.3 Operations.......................................................................................................................19 3.3.1 WRITE Operation ...............................................................................................19 3.3.2 READ Operation..................................................................................................20 3.3.3 SEARCH Operation ............................................................................................21 3.4 Match-Line Schemes......................................................................................................23 3.4.1 Conventional Matchline Schemes.......................................................................23 3.5 Summary........................................................................................................................25 Chapter 4 .........................................................................................................................................27 Low Power CAM......................................................................................................................27 4.1 Power Consumption........................................................................................................28 I 4.1.1 Dynamic Power Consumption ............................................................................28 4.1.2 Static Power Consumption..................................................................................29 4.1.3 Short Circuit Power Consumption.....................................................................30 4.1.4 Total Power Consumption...................................................................................31 4.2 Low Power Design for CAM..........................................................................................32 4.2.1 Active Low CAM..................................................................................................32 4.2.2 Control-Gatedd CAM..........................................................................................33 4.2.3 Selective Precharging CAM................................................................................35 4.2.4 Precomputation-Based CAM..............................................................................36 4.2.5 Serial-Parallel Comparison CAM ......................................................................37 4.2.6 Divided Matching Line Circuit for CAM..........................................................38 4.5 Summary.........................................................................................................................39 Chapter 5 .........................................................................................................................................40 Proposed Low Power CAM Circuit........................................................................................40 5.1 Introduction of Current-Race........................................................................................40 5.2 Positive-Feedback Match Line Sense Amplifiers.........................................................42 5.3 Proposed Active-Feedback MLSA ................................................................................46 5.4 Simulation Results...........................................................................................................49 5.4.1 Discussion and Comparison ...................................................................................50 5.5 Summary.........................................................................................................................53 Chapter 6 .........................................................................................................................................54 Conclusions..............................................................................................................................54 References........................................................................................................................................56 | |
dc.language.iso | en | |
dc.title | 低功率內容可定址記憶體之設計與分析 | zh_TW |
dc.title | Design and Analysis of Low Power Content Addressable Memory | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李鴻璋,張孟洲,張延任,蔡坤霖 | |
dc.subject.keyword | 內容可定址記憶體,低功率,相關性不匹配,正回授,節省電流, | zh_TW |
dc.subject.keyword | Content-Addressable Memory (CAM),low power,mismatch dependent,positive feedback,current saving, | en |
dc.relation.page | 59 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2008-06-25 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
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