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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 吳安宇(An-Yeu Wu) | |
dc.contributor.author | Chun-Yu Chen | en |
dc.contributor.author | 陳俊諭 | zh_TW |
dc.date.accessioned | 2021-06-08T07:03:15Z | - |
dc.date.copyright | 2009-02-03 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-01-22 | |
dc.identifier.citation | Reference
[1] C. Berrou, M. Jezequel, C. Douillard, and S. Kerouedan, 'The advantages of non-binary turbo codes,' in Proc. IEEE Information Theory Workshop, 2001, pp. 61-63. [2] C. Berrou, A. Glavieux, and P. Thitimajshima, 'Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1,' in Proc. IEEE Int. Conf. Commun. (ICC), vol.2, 1993, pp. 1064-1070. [3] C. Berrou and M. Jezequel, 'Non-binary convolutional codes for turbo coding,' Electron. Lett., vol. 35, pp. 39-40, 1999. [4] Http://en.wikipedia.org/wiki/4G [5] Nitin S. Choubey and Madan U. Kharat, “Overview of 3G and WiMAX Technology,“ in Pacific Journal of Science and Technology, vol.9, no.10, May 2008. [6] In-Stat/MDR report, “The Road to 4G: LTE and WiMAX Lead the Way Worldwide”, Oct 2008. [7] PracTel Inc. report, “The 4G Era: Mobile WiMAX and Long Term Evolution: Competitors or Friends - Technology and Markets Assessment”, May 2008. [8] (Online) http://www.3gpp.org/ [9] (Online) http://www.wimaxforum.org/home/ [10] M. Bickerstaff, L. Davis, C. Thomas, D. Garrett, and C. Nicol, 'A 24Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless,' in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), vol.1, 2003, pp. 150-484. [11] S. Myoung-Cheol and P. In-Cheol, 'A programmable turbo decoder for multiple 3G wireless standards,' in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), vol.1, 2003, pp. 154-484. [12] J.-H. Kim and I.-C. Park, 'A 50Mbps double-binary turbo decoder for WiMAX based on bit-level extrinsic information exchange,' in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), 2008, pp. 305-308. [13] L. Bahl, J. Cocke, F. Jelinek, and J. Raviv, 'Optimal decoding of linear codes for minimizing symbol error rate (Corresp.),' IEEE Trans. Inf. Theory, vol. 20, pp. 284-287, 1974. [14] P. Robertson, E. Villebrun, and P. Hoeher, 'A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain,' in Proc. IEEE Int. Conf. Commun. (ICC), vol.2, 1995, pp. 1009-1013. [15] A. J. Viterbi, 'An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes,' IEEE J. Sel. Areas Commun., vol. 16, pp. 260-264, 1998. [16] H. Dawid, G. Gehnen, and H. Meyr, 'Map channel decoding: Algorithm and VLSI architecture,' in Proc. Workshop on VLSI Signal Processing, vol. VI, 1993, pp. 141-149. [17] K. Ji-Hoon and P. In-Cheol, 'Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding,' in Proc. IEEE Int. Symp. Circuits and Systems, (ISCAS), 2007, pp. 1325-1328. [18] K. Ji-Hoon and P. In-Cheol, 'Duo-binary circular turbo decoder based on border metric encoding for WiMAX,' in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), 2008, pp. 109-110. [19] J. B. Anderson and S. M. Hladik, 'Tailbiting MAP decoders,' IEEE J. Sel. Areas Commun., vol. 16, pp. 297-302, 1998. [20] C. Zhan, T. Arslan, A. T. Erdogan, and S. MacDougall, 'An Efficient Decoder Scheme for Double Binary Circular Turbo Codes,' in Proc. IEEE Int. Conf. Acoustics, Speech and Signal Processing (ICASSP), 2006, pp. IV-IV. [21] R. Dobkin, M. Peleg, and R. Ginosar, 'Parallel VLSI architecture for MAP turbo decoder,' in Proc. The 13th IEEE Int. Symp. Personal, Indoor and Mobile Radio Commun., vol.1, 2002, pp. 384-388. [22] 3GPP Technical Specification TS 36.202 V8.3.0“Multiplexing and Channel Coding (FDD) (Release 8),” May, 2008. [23] Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems, IEEE Std 802.16™-2005, IEEE Standard for Local and metropolitan area networks, IEEE, Dec. 2005. [24] R. Asghar and D. Liu, 'Dual standard re-configurable hardware interleaver for turbo decoding,' in Proc. The 3rd Int. Symp. Wireless Pervasive Computing (ISWPC), 2008, pp. 768-772. [25] C.–H. Lin, C.-Y. Chen and A.-Y. Wu, 'High-throughput 12-mode CTC decoder for WiMAX standard,' in Proc. IEEE Int. Symp. VLSI Design, Automation and Test (VLSI-DAT), 2008, pp. 216-219. [26] A. Nimbalker, Y. Blankenship, B. Classon, and T. K. Blankenship, 'ARP and QPP Interleavers for LTE Turbo Coding,' in Proc. IEEE Wireless Commun. and Networking Conf. (WCNC), 2008, pp. 1032-1037. [27] M.-C. Hsu and C.-Y. Lee, “An Area-efficient double-binary CTC decoder for WiMAX applications,” Master thesis, National Chiao-Tung University, July, 2008. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26220 | - |
dc.description.abstract | 由於無線設備使用者對於多媒體影音傳輸的需求與日俱增,對於未來的無線廣域網路,如3GPP-LTE與WiMAX系統,都已訂製符合高傳輸速率(100Mbps)的需求。近年來為了增加傳輸的可靠度,這些無線廣域網路系統開始納入更先進的通道碼技術。其中,1993年由Berrou等人所發現的單二元迴旋渦輪碼,已經被證實具有接近向農邊界的解碼效能。接著在1999年,在一時間編解碼兩筆位元的雙二元迴旋渦輪碼被提出,並被認為具有更佳的編碼增益。此兩種形式的渦輪碼已分別為3GPP-LTE系統與WiMAX系統所採用。
此篇論文的主要目標即是設計一套適用於未來無線廣域網路的高吞吐量且可重組化的迴旋渦輪解碼器. 此設計具備下列特色: 1) 針對迴旋渦輪解碼器的兩個主要組成單元:最大事後機率解碼器與交錯器提出新架構來提升吞吐量。2) 利用單二元迴旋渦輪碼與雙二元迴旋渦輪碼演算法上的運算相似性,設計可重組化的最大事後機率解碼器與交錯器以支援此兩種不同形式的迴旋渦輪碼。3) 以3GPP-LTE與WiMAX系統的迴旋渦輪碼規格為設計標的。合成結果證實在少於10%的硬體多於成本下,可使最大事後機率解碼器達到支援兩種迴旋渦輪碼演算法的目標。交錯器則可使用64.2%的硬體成本產生3GPP-LTE與WiMAX系統所要的交錯位置。 最後,將所提出的最大事後機率解碼器與交錯器整合至迴旋渦輪解碼器中。在晶片實現上,所提出的迴旋渦輪解碼器使用TSMC 0.13 μm 1P8M的先進製程來實現,晶片面積為7.02 mm2,且最高可操作的頻率為147 MHz。此解碼器可以支援3GPP-LTE系統與WiMAX系統共34種不同的操作模式,並且可達到260.2 Mbps的最高資料傳輸率,符合未來無線廣域網路的傳輸需求。 | zh_TW |
dc.description.abstract | With the rapid growth of multimedia service demand, the data-rate requirement will be higher than 100 Mbps for future wireless WAN, such as 3GPP-LTE and WiMAX systems. In recent years, these wireless WAN systems have adopted advanced channel coding schemes in order to increase transmission reliability. Among them, the single-binary convolutional turbo code (SB-CTC) introduced by Berrou et al. in 1993 had been proved to have decoding performance close to the Shannon limit. Then, in 1999, the double-binary CTC (DB-CTC) was proposed to encode/decode two bits per time and yield to better coding gain compared with the SB-CTC. The SB- and DB-CTC schemes have been adopted in 3GPP-LTE and WiMAX systems, respectively.
The goal of this thesis is to design a high-throughput reconfigurable CTC decoder that can be used in future wireless WAN systems. The features are 1) propose new architecture for the MAP decoder and interleaver, the two main components of the CTC decoder, to achieve high-throughput requirement, 2) design the reconfigurable MAP decoder and interleaver based on the computational similarity between SB-CTC and DB-CTC decoding algorithms, and 3) target the CTC specification of 3GPP-LTE and WiMAX systems. The synthesis results show that the hardware overhead for the MAP decoder to support both CTC decoding algorithms is less than 10%. And only 64.2% hardware resource is required to generate the interleaved address of both 3GPP-LTE and WiMAX systems. Finally, the proposed MAP decoder and interleaver are embedded into a CTC decoder. By using TSMC 0.13 μm 1P8M CMOS process, the proposed CTC decoder is implemented in a chip at 147 MHz maximum operating frequency with core size of 7.02 mm2. The implemented decoder can support 34-mode CTC decoding for both 3GPP-LTE and WiMAX systems. The maximum throughput rate can achieve 260.2 Mbps which satisfies the data-rate requirement of the future wireless WAN systems. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T07:03:15Z (GMT). No. of bitstreams: 1 ntu-98-R95943173-1.pdf: 2772159 bytes, checksum: 1a52482af787d0dabdad609834b3c095 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | Contents
Abstract V Contents VII List of Figures IX List of Tables XI Chapter 1 Introduction 1 1.1 Introduction of Convolutional Turbo Codes 1 1.2 Motivation & Goal 2 1.3 Thesis Organization 5 Chapter 2 Review of Convolutional Turbo Codes 7 2.1 Typical CTC Encoder/Decoder Structure 7 2.2 MAP Decoding Algorithm 9 2.3 Timing Chart of MAP Decoding 14 Chapter 3 High-Throughput Dual-Mode MAP Decoder Design 17 3.1 Warm-up Free Parallel-Window MAP Decoding 17 3.2 Key Components Design for Dual-Mode MAP Decoder 22 Chapter 4 Parallel Dual-Standard Interleaver Design 37 4.1 Introduction of Interleaver 37 4.2 Parallel Interleaver Design 40 4.3 Dual-Standard Address Generator Design 45 4.4 Experimental Results 48 Chapter 5 VLSI Design of High-Throughput 34-Mode CTC Decoder 53 5.1 Throughput Analysis 54 5.2 Determination of Wordlength 55 5.3 VLSI Architecture of Proposed 34-Mode CTC Decoder 57 5.4 Chip Implementation 58 Chapter 6 Conclusions 63 Reference 65 | |
dc.language.iso | zh-TW | |
dc.title | 適用於未來無線廣域網路的高吞吐量可重組化迴旋渦輪解碼器設計 | zh_TW |
dc.title | High-Throughput Reconfigurable Convolutional Turbo Decoder Design for Future Wireless WAN | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 闕志達(Tzi-Dar Chiueh),陳光禎(Kwang-Cheng Chen),蔡佩芸(Pei-Yun Tsai),丁邦安(Pang-An Ting) | |
dc.subject.keyword | 迴旋渦輪碼,高吞吐量,可重組化,平行化, | zh_TW |
dc.subject.keyword | Convolutional Turbo Code,high-throughput,reconfigurable,parallel, | en |
dc.relation.page | 67 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2009-01-22 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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