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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳少傑 | |
| dc.contributor.author | Ying-Cherng Lan | en |
| dc.contributor.author | 籃英誠 | zh_TW |
| dc.date.accessioned | 2021-06-08T07:02:02Z | - |
| dc.date.copyright | 2011-08-18 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-08-15 | |
| dc.identifier.citation | [1] F. N. Najm, “A Survey of Power Estimation Techniques in VLSI Circuits,” IEEE Transactions on Very Large Scale Integrations Systems, vol. 2, no. 4, pp. 446-455, December 1994.
[2] R. Ho, K. W. Mai, and M. A. Horowitz, “The Future of Wires,” Proceedings of the IEEE, vol. 89, no. 4, pp. 490-504, April 2001. [3] L. Benini and G. De Micheli, “Networks on Chips: a New SoC Paradigm,” IEEE Transactions on Computers, vol. 35, no. 4, pp. 70-78, January 2002. [4] W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004. [5] W. J. Dally and B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks,” in Proceedings of the Design Automation Conference, pp. 684-689, June 2001. [6] ARM, AMBA Specification Rev 2.0, ARM Limited, 1999. [7] IBM, 32-bit Processor Local Bus Architecture Specification Version 2.9, IBM Corporation. [8] R. Hegde and N. R. Shanbhag, 'Toward Achieving Energy Efficiency in Presence of Deep Submicron Noise,' IEEE Transactions on Very Large Scale Integration Systems, vol. 8, no. 4, pp. 379-391, August 2000. [9] A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Oberg, M. Millberg, and D. Lindvist, “Network-on-Chip: an Architecture for Billion Transistor Era,” in Proceedings of the IEEE NorChip Conference, pp. 1-8, 2000. [10] C. Constantinescu, “Trends and Challenges in VLSI Circuit Reliability,” IEEE Micro, vol. 23, no. 4, pp. 14-19, July 2003. [11] N. Cohen, T. S. Sriram, N. Leland, S. Butler, and R. Flatley, “Soft Error Considerations for Deep-Submicron CMOS Circuit Applications,” in Proceedings of the International Electron Devices Meeting Technical Digest, pp. 315-318, December 1999. [12] P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi, “Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic,” in Proceeding of the Dependable Systems and Networks, pp. 389-398, June 2002. [13] S. Kumar, A. Jantsch, J. P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani, “A Network-on-Chip Architecture and Design Methodology,” in Proceedings of the International Symposium on Very Large Scale Integration, pp. 105-112, April 2000. [14] C. Grecu and M. Jones, “Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures,” IEEE Transactions on Computers, vol. 54, no. 8, pp. 1025-1040, August 2005. [15] A. M. Rahmani, M. Daneshtalab, A. A. Kusha, S. Safari, and M. Pedram, “Forecasting-Based Dynamic Virtual-channels Allocation for Power Optimization of Network-on-Chips,” in Proceedings of the International Conference on VLSI Design, pp. 151-156, January 2009. [16] N Kavaldjiev, G. Smit, and P. Jansen, “A Virtual-channel Router for on-Chip Networks,” in Proceedings of the System-on-Chip Conference, pp. 289-293, September 2004. [17] W. J. Dally, “Virtual Channel Flow Control,” IEEE Transactions on Parallel and Distributed Systems, vol. 3, no. 2, pp. 194-205, March 1992. [18] E. Rijpkema, K. G. W. Goossens, A. Radulescu, J. Dielissen, J. V. Meerbergen, P. Wielage, and E. Waterlander, “Trade-offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks-on-Chip,” in Proceedings of the Design Automation and Test in Europe Conference, pp. 350-355, March 2003. [19] H. S. Wang, L. S. Peh and S. Malik, “A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers,” IEEE Micro, vol. 23, no. 1, pp. 26-35, Jan./Feb. 2003. [20] R. Mullins, A. West, and S. Moore, “Low-Latency Virtual-Channel Routers for On-Chip Networks,” in Proceedings of the International Symposium on Computer Architecture, pp. 188-197, June 2004. [21] K. Kim, S. J. Lee, K. Lee, and H. J. Yoo, “An Arbitration Look-ahead Scheme for Reducing End-to-End Latency in Networks-on-Chip,” in Proceedings of the International Symposium on Circuits and Systems, pp. 2357-2360, May 2005. [22] P. Guerrier and A. Greiner, “A Generic Architecture for On-Chip Packet-Switched Interconnections,” in Proceedings of the Design Automation and Test in Europe Conference, pp. 250-256, Mar. 2000. [23] M. R. Garey and D. S. Johnson, Computers and Intractability: a Guide to the Theory of NP-Completeness, Freeman and Company, 1979. [24] M. Lis, M. H. Cho, K. S. Shim, and S. Devadas, “Path-Diverse In-Order Routing,” in Proceedings of the International Conference on Green Circuits and Systems, pp. 311-316, June 2010. [25] Y. Tamir and G. L. Frazier, “Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches,” IEEE Transactions on Computers, vol. 41, no. 6, pp. 725-737, June 1992. [26] E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, “Routing Table Minimization for Irregular Mesh NoCs,” in Proceedings of the Design Automation and Test in Europe Conference, pp. 1-6, April 2007. [27] S. Murali, D. Atienza, L. Benini, and G. De Micheli, “A Multi-Path Routing Strategy with Guaranteed In-Order Packet Delivery and Fault-Tolerance for Network-on-Chip,” in Proceedings of the Design Automation Conference, pp. 845-848, July 2006. [28] M. Lis, K. S. Shim, M. H. Cho, and S. Devadas, “Guaranteed In-Order Packet Delivery using Exclusive Dynamic Virtual-channel Allocation,” Massachusetts Institute of Technology, Technical Report, CSAIR-TR-2009-036, August 2009. [29] M. Daneshtalab, A. A. Kusha, A. Sobhani, Z. Navabi, M. D. Mottaghi, and O. Fatemi, “Ant Colony Based Routing Architecture for Minimizing Hot Spots in NOCs,” in Proceedings of the Annual Symposium on Integrated Circuits and System Design, pp. 56-61, September 2006. [30] J. Hu and R. Marculescu, “DyAD–Smart Routing for Networks-on-Chip,” in Proceedings of the Design Automation Conference, pp. 260-263, June 2004. [31] C. J. Glass and L.M. Ni, “The Turn Model for Adaptive Routing”, Journal of ACM, vol. 41, no. 5, pp. 874-902, September 1994. [32] G. M. Chiu, “The Odd-Even Turn Model for Adaptive Routing,” IEEE Transactions on Parallel and Distributed Systems, vol. 11, no. 7, pp. 729-738, July 2000. [33] G. Ascia, V. Catania, M. Palesi, and D. Patti, “Neighbors On-Path: A New Selection Strategy for On-Chip Networks,” in Proceedings of the IEEE Workshop on Embedded Systems for Real Time Multimedia, pp. 79-84, October 2006. [34] M. Li, Q.A. Zeng, and W. B. Jone, “DyXY - a Proximity Congestion-Aware Deadlock-Free Dynamic Routing Method for Network on Chip,” in Proceedings of the Design Automation Conference, pp.849-852, July 2006. [35] M. A. Yazdi, M. Modarressi, and H. S. Azad, “A Load-Balanced Routing Scheme for NoC-Based System-on-Chip,” in Proceedings of the Workshop on Hardware and Software Implementation and Control of Distributed MEMS, pp. 72-77, June 2010. [36] E. Nilsson, M. Millberg, J. Oberg, and A. Jantsch, “Load Distribution with the Proximity Congestion Awareness in a Network-on-Chip,” in Proceedings of the Design Automation and Test in Europe Conference, pp.1126-1127, December 2003. [37] J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan, and C. R. Das, “A Low Latency Router Supporting Adaptivity for on-Chip Interconnects,” in Proceedings of the Design Automation Conference, pp. 559-564, June 2005. [38] D. Wu, B. M. Al-Hashimi, and M. T. Schmitz, “Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection,” in Proceedings of the Asia and South Pacific Design Automation Conference, pp. 36-41, January 2006. [39] M. Millberg, E. Nilsson, R. Thid, and A. Jantsch, “Guaranteed Bandwidth using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip,” in Proceedings of the Design Automation and Test in Europe Conference, pp. 890-895, February 2004. [40] K. Goossens, J. Dielissen, and A. Radulescu, “The Æthereal Network on Chip: Concepts, Architectures, and Implementations,” IEEE Design & Test of Computers, vol. 22, no. 5, pp. 414-421, October 2005. [41] P. Vellanki, N. Banerjee, and K. S. Chatha, “Quality-of-Service and Error Control Techniques for Mesh-Based Network-on-Chip Architectures,” ACM Very Large Scale Integration Journal, vol. 38, no. 3, pp. 353-382, January 2005. [42] N. Kavaldjiev, G. J. M. Smit, P. G. Jansen, and P. T. Wolkotte, “A Virtual-channel Network-on-Chip for GT and BE Traffic,” in Proceedings of the Annual Symposium on Emerging VLSI Technologies and Architectures, pp. 211-216, March 2006. [43] E. Bolotin, I, Cidon, R. Ginosar, and A. Kolodny, “QNoC: QoS Architecture and Design Process for Network-on-Chip,' Elsevier Journal of System Architecture, vol. 50, no. 2-3, pp. 105-128, February 2004. [44] M. Dall’osso, G. Biccari, L. Giovannini, D. Bertozzi, and L. Benini, “Xpipes: a Latency Insensitive Parameterized Network-on-Chip Architecture for Multiprocessor SoCs,” in Proceedings of the International Conference on Computer Design, pp. 536-539, October 2003. [45] D. Bertozzi and L. Benini, “Xpipes: a Network-on-Chip Architecture for Gigascale System-on-Chip,” IEEE Circuits and Systems Magazine, vol. 4, no. 2, pp. 18-31, April 2004. [46] M. D. Harmanci, N. P. Escudero, Y. Leblebici, and P. Ienne, “Providing QoS to Connection-Less Packet-Switched NoC by Implementing DiffServ Functionalities,” in Proceedings of the International Symposium on System-on-Chip, pp. 37-40, November 2004. [47] A. Mello, L. Tedesco, N. Calazans, and F. Moraes, “Evaluation of Current QoS Mechanisms in Networks-on-Chip,” in Proceedings of the International Symposium on System-on-Chip, pp. 1-4, November 2006. [48] Z. Guz, E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, “Efficient Link Capacity and QoS Design for Network-on-Chip,” in Proceedings of the Design Automation and Test in Europe Conference, pp. 1- 6, March 2006. [49] P. Vellanki, N. Banerjee, and K. S. Chatha, “Quality-of-Service and Error Control Techniques for Network-on-Chip Architecture,” in Proceedings of the Great Lakes Symposium on VLSI, pp. 45-50, April 2004. [50] M. D. Harmanci, N. P. Escudero, Y. Leblebici, and P. Ienne, “Quantitative Modeling and Comparison of Communication Schemes to Guarantee Quality-of-Service in Networks-on-Chip,” in Proceedings of the International Symposium on Circuits and Systems, pp. 1782-1785, May 2005. [51] T. Bjerregaard and J. Sparso, “A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip,” in Proceedings of the Design Automation and Test in Europe Conference, pp. 1226-1231, March 2005. [52] D. Bertozzi, A. Jalabert, M. Srinivasan, R. Tamhankar, S. Sterqiou, L. Benini and G. De Micheli, “NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-chip,” IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 2, pp. 113-129, February 2005. [53] T. Bjerregaard and S. Mahadevan, “A Survey of Research and Practices of Network-on-Chip,” ACM Computing Surveys, vol. 38, no. 1, pp. 1-51, March 2006. [54] U. Orgas, J. Hu, and R. Marculescu, “Key Research Problems in NoC Design: A Holistic Perspective,” in Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, pp 69-74, September 2005. [55] R. Marculescu, U. Y. Ogras, L. S. Peh, N. E. Jerger, and Y. Hoskote, “Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 3-21, January 2009. [56] H. G. Lee, N. Chang, U. Y. Ogras, and R. Marculescu, “On-Chip Communication Architecture Exploration: A Quantitative Evaluation of Point-to-Point, Bus and Network-on-Chip Approaches,” ACM Transactions on Design Automation of Electronic Systems, vol. 12, no. 3, pp. 1-20, August 2007. [57] J. D. Owens, W. J. Dally, R. Ho, D. N. Jayasimha, S. W. Keckler, and L. S. Peh, “Research Challenges for On Chip Interconnection Networks,” IEEE Micro, vol. 27, no. 5, pp. 96-108, November 2007. [58] J. Lillis and C. Cheng, “Timing Optimization for Multisource Nets: Characterization and Optimal Repeater Insertion,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 3, pp. 322-331, Mar. 1999. [59] S. Bobba and I. N. Hajj, “High-Performance Bidirectional Repeaters,” in Proceedings of the Great Lakes Symposium on Very Large Scale Integration, pp. 53-58, March 2000. [60] A. Nalamalpu, S. Srinivasan, and W. P. Burleson, “Boosters for Driving Long Onchip Interconnects – Design Issues, Interconnect Synthesis, and Comparison with Repeaters,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 1, pp. 50-62, January 2002. [61] H. Ito, M. Kimura, K. Miyashita, T. Ishii, K. Okada, and K. Masu, “A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications,” IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 1020-1029, April 2008. [62] M. A. A. Faruque, T. Ebi, and J. Henkel, “Configurable Links for Runtime Adaptive On-Chip Communication,” in Proceedings of the Design Automation and Test in Europe Conference, pp. 256-261, April 2009. [63] M. H. Cho, M. Lis, K. S. Shim, M. Kinsy, T. Wen, and S. Devadas, “Oblivious Routing in On-Chip Bandwidth-Adaptive Networks,” in Proceedings of the Parallel Architectures and Compilation Techniques, pp. 181-190, September 2009. [64] Y. C. Lan, S. H. Lo, Y. C. Lin, Y. H. Hu, and S. J. Chen, “BiNoC: A Bidirectional NoC Architecture with Dynamic Self-Reconfigurable Channel,” in Proceedings of the International Symposium on Network-on-Chip, pp. 266-275, May 2009. [65] L. S. Peh and W. J. Dally, “A Delay Model and Speculative Architecture for Pipelined Routers,” in Proceedings of the International Symposium on High-Performance Computer Architecture, pp. 255-266, January 2001. [66] J. D. Owens, W. J. Dally, R. Ho, D. N. Jayasimha, S. W. Keckler and L. S. Peh, “Research Challenges for On Chip Interconnection Networks,” IEEE Micro, vol. 27, no. 5, pp. 96-108, Nov. 2007. [67] D. C. Gazis, Traffic Science, John Wiley and Sons, 1974. [68] R. Dick, “Embedded System Synthesis Benchmark Suites (E3S),” http://ziyang.eecs.umich.edu/~dickrp/e3s/, Accessed January 2011. [69] L. Shang, L. S. Peh, and N. K. Jha, “Powerherd: a Distributed Scheme for Dynamically Satisfying Peak-Power Constraints in Interconnection Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 1, pp. 92-110, January 2006. [70] A. Banerjee, P. T. Wolkotte, R. D. Mullins, S. W. Moore, and G. J. M. Smit, “An Energy and Performance Exploration of Network-on-Chip Architectures,” IEEE Transactions on Very Large Scale Integration Systems, vol. 17, no. 3, pp. 319-329, March 2009. [71] D. A. Menasce and R. R. Muntz, “Locking and Deadlock Detection in Distributed Data Base,” IEEE Transactions on Software Engineering, vol. SE-5, no. 3, pp. 195-202, May 1979. [72] International Technology Roadmap for Semiconductors: Executive Summary, Semiconductor Industry Association, 2007. [73] F. Angiolini, P. Meloni, S. M. Carta, L. Raffo, and L. Benini, “A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 3, pp. 421-434, March 2007. [74] I. Hatirnaz, S. Badel, N. Pazos, Y. Leblebici, S. Murali, D. Atienza, and G. De Micheli, “Early Wire Characterization for Predictable Network-on-Chip Global Interconnects,” in Proceedings of the International Workshop on System Level Interconnect Prediction, pp. 57-64, March 2007. [75] A. Pullini, F. Angiolini, S. Murali, D. Atienza, G. De Micheli, and L. Benini, “Bringing NoCs to 65nm,” IEEE Micro, vol. 27, no. 5, pp. 75-85, September 2007. [76] M. Zhang and C. S. Choy, “Low-Cost VC Allocator Design for Virtual-channel Wormhole Routers in Network-on-Chip,” in Proceedings of the International Symposium on Networks-on-Chip, pp. 207-208, April 2008. [77] R. Guerin and V. Peris, “Quality-of-Service in Packet Networks: Basic Mechanisms and Directions,” in Proceedings of the Computer Networks, pp. 169-179, February 1999. [78] C. A. Nicopoulos, D. Park, J. Kim, N. Vijaykrishnan, M. S. Yousif, and C. R. Das, “ViChaR: a Dynamic Virtual-channel Regulator for Network-on-Chip Routers,” in Proceedings of the International Symposium on Microarchitecture, pp. 333-346, December 2006. [79] J. Diemer and R. Ernst, “Back Suction: Service Guarantees for Latency-Sensitive On-Chip Networks,” in Proceedings of the International Symposium on Networks-on-Chip, pp. 155-162, May 2010. [80] T. Marescaux and H. Corporaal, “Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GT,” in Proceedings of the Design Automation Conference, pp. 116-121, June 2007. [81] J. Diemer, R. Ernst, and M. Kauschke, “Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip,” in Proceedings of the Asia and South Pacific Design Automation Conference, pp. 529-534, January 2010. [82] M. Kistler, M. Perrone, and F. Petrini, “Cell Multiprocessor Communication Network: Built for Speed,” IEEE Micro, vol. 26, no. 3, pp. 10-23, May 2006. [83] L. Seiler, D. Carmean, E. Sprangle, T. Forsyth, P. Dubey, S. Junkins, A. Lake, R. Cavin, R. Espasa, E. Grochowski, T. Juan, M. Abrash, J. Sugerman, and P. Hanrahan, “Larrabee: A Many-Core x86 Architecture for Visual Computing,” IEEE Micro, vol. 29, no. 1, pp. 10-21, January 2009. [84] D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown, and A. Agarwal, “On-Chip Interconnection Architecture of the Tile Processor,” IEEE Micro, vol. 27, no. 5, pp. 15-31, September 2007. [85] J. Howard, S. Dighe, Y. Hoskote, S. Vangal, D. Finan, G. Ruhl, D. Jenkins, H. Wilson, N. Borkar, G. Schrom, F. Pailet, S. Jain, T. Jacob, S. Yada, S. Marella, P. Salihundam, V. Erraguntla, M. Konow, M. Riepen, G. Droege, J. Lindemann, M. Gries, T. Apel, K. Henriss, T. L. Larsen, S. Steibl, S. Borkar, V. De, R. V. D. Wijngaart, and T. Mattson, “A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS,” in Proceedings of International Solid-State Circuits Conference Digest of Technical Papers, pp. 108-109, February 2010. [86] M. A. A. Faruque, G. Weiss, and J. Henkel, “Bounded Arbitration Algorithm for QoS-Supported on-Chip Communication,” in Proceedings of International Conference on Hardware/Software Codesign and System Synthesis, pp. 76-81, October 2006. [87] K. S. Shim, M. H. Cho, M. Kinsy, T. Wen, M. Lis, G. E. Suh, and S. Devadas, “Static Virtual Channel Allocation in Oblivious Routing,” in Proceedings of the International Symposium on Network-on-Chip, pp. 38-43, May 2009. [88] A. M. Rahmani, M. Daneshtalab, P. Liljeberg, and H. Tenhunen, “Power-Aware NoC Router using Central Forecasting-Based Dynamic Virtual Channel Allocation,” in Proceedings of the International Symposium on Circuits and Systmes, pp. 3224-3227, May 2010. [89] A. M. Rahmani, M. Daneshtalab, A. A. Kusha, and S. Safari, “Power Efficient Switches with Dynamic Virtual Channel Allocation for Network-on-Chips,” in Proceedings of the International Conference on Innovations in Information Technology, pp. 121-125, December 2008. [90] A. M. Rahmani, M. Daneshtalab, A. A. Kusha, S. Safari, and M. Pedram, “Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips,” in Proceedings of the International Conference on VLSI Design, pp. 151-156, January 2009. [91] L. Mingche, G. Lei, S. Wei, and W. Zhiying, “Escaping from Blocking: A Dynamic Virtual Channel for Pipelined Routers,” in Proceedings of the International Conference on Complex, Intelligent and Software Intensive Systems, pp. 795-800, March 2008. [92] W. J. Dally and C. L. Seitz, “The Torus Routing Chip,” Journal of Distributed Computing, vol. 1, no. 4, pp. 187-196, January 1986. [93] P. Kermani and L. Kleinrock, “Virtual Cut-Through: A New Computer Communication Switching Technique,” Computer Networks, vol. 3, no. 4, pp. 267-286, September 1979. [94] L. S. Peh and W. J. Dally, “A Delay Model for Router Microarchitectures,” IEEE Micro, vol. 21, no. 1, pp.26-34, January 2001. [95] W. J. Dally and C. L. Seitz, “Deadlock-Free Message Routing in Multiprocessor Interconnection Networks,” IEEE Transactions on Computers, vol. C-36, no. 5, pp. 547-553, May 1987. [96] Y. M. Boura and C. R. Das, “Performance Analysis of Buffering Schemes in Wormhole Routers,” IEEE Transactions on Computers, vol. 46, no. 6, pp. 687-694, June 1997. [97] M. Rezazad and H. S. Azad, “The Effect of Virtual Channel Organization on the Performance of Interconnection Network,” in Proceedings of the International Parallel and Distributed Processing Symposium, pp. 1-8, April 2005. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26174 | - |
| dc.description.abstract | 本篇論文提出了一個雙向網路晶片的架構以增進晶片上資料傳輸之效能。在此雙向網路晶片中，每一傳輸通道允許動態自我改變資料的傳輸方向。而這新增的彈性可適用於大部分傳統的網路晶片並保証較好的頻寬使用率、較低的資料傳輸延遲、及較高的資料消耗率。
此雙向網路晶片使用一個新的晶片上路由器設計來達到動態調變雙向資料流的目的。資料流方向的改變由一個使用一對有限狀態機之通道方向控制演算法來決定。此有限狀態機不只提供了較高的效能，並可避免資料死結及飢餓的發生。除此之外，考慮服務質量的演算法也被整合於雙向通道控制邏輯中，以達到不同的資料服務質量需求。而藉由我們所實現的低功耗虛擬通道管理機制，雙向網路晶片可以在減少前端緩衝佇列阻塞的同時減少虛擬通道的使用量，進而在維持實作成本的同時達到高效能的目的。 最後，大量時脈精準的摸擬以人工合成資料流及實際應用資料流來評估雙向網路晶片之效能。這些結果都顯示了雙向網路晶片相較於傳統單向網路晶片具有顯著的效能優勢。而在實作上，雙向網路晶片也能有效地利用增加頻寬使用的彈性，減少了路由器上實際需要的資料緩衝暫存器用量，並達到晶片功耗及面積上的改善。 | zh_TW |
| dc.description.abstract | A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed in this Dissertation to enhance the performance of on-chip communication while keeping the implementation cost efficient. In a BiNoC, each communication channel allows to be dynamically self-reconfigured to transmit flits in either direction. This added flexibility can be easily fitted into most of the state-of-the-art conventional NoC designs and promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate.
The novel on-chip BiNoC router architecture is developed to support dynamic self-reconfiguration in the bidirectional traffic flow. The flow direction at each channel is decided by a channel-direction control protocol that is high-performance, free of deadlock, and free of starvation. In addition, a QoS-aware bidirectional arbitration scheme is integrated to ensure various service requirements such as best-effort, guaranteed-service, and guaranteed-throughput. Furthermore, with our proposed novel virtual-channel management, BiNoC can reduce head-of-line blocking without increasing the number of virtual-channels (VCs) thus improves performance while keeping low implementation cost. Experimental results using both synthetic traffic patterns and E3S benchmarks verified that the proposed BiNoC architecture can significantly reduce the traffic delivery latency at all levels of traffic injection rates. Besides, the proposed QoS control mechanism can significantly improve the channel utilization for latency-sensitive traffics while keeping sufficient bandwidth for throughput-sensitive ones. Finally, it is very encouraging that the BiNoC can improve traffic delivering efficiency and achieve the goal of power and area saving by increasing bandwidth utilization flexibility and reducing the physical volume of buffer requirements. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T07:02:02Z (GMT). No. of bitstreams: 1 ntu-100-F94943068-1.pdf: 5109513 bytes, checksum: bf172c85c350a7a7e8d6547189956909 (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | ABSTRACT ................................................i
LIST OF FIGURES ......................................ix LIST OF TABLES ....................................xiii CHAPTER 1. INTRODUCTION...........................1 1.1 Communications-Centric Design Concept...........1 1.1.1 Multi-Processor System-on-Chip..................2 1.1.2 Conventional on-Chip Communication Scheme.......2 1.1.3 Emergence of Network-on-Chip....................4 1.2 Concept of Network-on-Chip......................4 1.3 Layers in a Network-on-Chip Design..............5 1.3.1 Physical Layer..................................6 1.3.2 Network Layer...................................6 1.3.3 Application Layer...............................8 1.4 Motivation and Dissertation Contribution........8 1.4.1 Motivation......................................9 1.4.2 Dissertation Contribution.......................9 1.5 Dissertation Organization......................11 CHAPTER 2. PRELIMINARIES.........................13 2.1 Background Knowledge...........................13 2.2 Conventional Network-on-Chip Architecture......14 2.3 Conventional Router Architecture...............15 2.4 Flow-Control Mechanism.........................17 2.4.1 Packet-Buffer Flow-Control.....................18 2.4.2 Wormhole Flow-Control Based Router.............18 2.4.3 Virtual-Channel Flow-Control Based Router......19 2.5 Routing and Arbitration Techniques.............21 2.5.1 Problem Decomposition..........................21 2.5.2 State-of-the-Art...............................22 2.6 Quality-of-Service Control.....................24 2.6.1 Connection-Oriented Scheme.....................24 2.6.2 Connection-Less Scheme.........................25 CHAPTER 3. BIDIRECTIONAL NOC ARCHITECTURE........27 3.1 Problem Description............................27 3.1.1 Motivational Example...........................28 3.1.2 Channel Bandwidth Utilization..................29 3.2 Bidirectional Channel..........................32 3.2.1 Design Requirements............................32 3.2.2 Related Works..................................33 3.3 BiNoC: Bi-directional NoC Router Architecture..34 3.3.1 BiNoC Router with Wormhole Flow-Control........34 3.3.2 BiNoC Router with Virtual-Channel Flow-Control.35 3.3.3 Reconfigurable Input/Output Ports..............37 3.3.4 Channel Control Module.........................38 3.3.5 Virtual-Channel Allocator......................39 3.3.6 Switch Allocator...............................40 3.4 Remarks........................................41 CHAPTER 4. BIDIRECTIONAL CHANNEL-DIRECTION CONTROL43 4.1 Inter-Router Transmission Scheme................43 4.2 Bidirectional Channel Routing Direction Control.44 4.2.1 High-Priority FSM Operations....................45 4.2.2 Low-Priority FSM Operations.....................46 4.2.3 Channel Authority Confliction...................47 4.3 Resource Contention.............................48 4.3.1 Inter-Router Starvation.........................48 4.3.2 Deadlock-Free Routing...........................50 4.4 Packet Ordering.................................54 4.5 Packet Transmission Interruption................54 4.6 Remarks.........................................57 CHAPTER 5. BINOC CHARACTERIZATION.................59 5.1 Experiments Setup...............................59 5.2 Synthetic Traffic Analysis......................61 5.2.1 Comparison between BiNoC and Conventional NoC...61 5.2.2 Performance under Equal Buffer Depth............63 5.2.3 Performance under Equal Buffer Size.............65 5.2.4 Bidirectional Channel Switching Probability.....66 5.2.5 Bandwidth Utilization Analysis..................67 5.2.6 Buffer Size Analysis............................69 5.2.7 Traffic Consumption Rate Analysis...............70 5.3 Experiments with Real Applications..............71 5.4 Implementation Details in terms of Area and Power 73 5.4.1 Area Measurement................................73 5.4.2 Power Measurement...............................74 5.5 Implementation Overheads........................77 5.5.1 Overhead in Bidirectional Channel Control Module 77 5.5.2 Overhead in ST Stage............................77 5.5.3 Overhead in Input Buffer Stage..................78 5.5.4 Overhead in Interconnection Wires...............82 5.6 Remarks.........................................82 CHAPTER 6. QOS SUPPORT FOR BINOC ARCHITECTURE.....83 6.1 QoS Control in NoCs.............................83 6.2 Typical Connection-Less QoS Mechanism for NoC...84 6.3 Motivational Example............................85 6.4 QoS Design for BiNoC Router.....................87 6.4.1 Prioritized VC Management and Inter-Router Arbitration..............................................87 6.4.2 Prioritized Deadlock-Free Routing Restriction...88 6.5 Inter-Router Transmission Scheme................89 6.6 QoS Design for BiNoC Channel-Direction Control 91 6.6.1 High-Priority FSM Operations....................92 6.6.2 Low-priority FSM Operations.....................94 6.7 Performance Evaluation..........................95 6.7.1 Experiments Setups..............................95 6.7.2 Synthetic Traffic Patterns......................96 6.7.3 Comparison between BiNoC_QoS and BiNoC_4VC......96 6.7.4 Comparison between BiNoC_QoS and NoC_QoS........98 6.7.5 Analysis of Prioritized Routing................100 6.7.6 Analysis of Consumption Rate...................101 6.7.7 Comparison between GS and BE Traffics..........102 6.8 Remarks........................................105 CHAPTER 7. THROUGHPUT-GUARANTEED DESIGN FOR BINOC 107 7.1 Throughput-Guaranteed Design in NoCs...........107 7.2 Throughput-Guaranteed Design for BiNoC Architecture............................................108 7.2.1 Channel Prioritization.........................109 7.2.2 Throughput Regulator...........................110 7.3 Inter-Router Transmission Scheme...............111 7.4 Throughput-Guaranteed Design for BiNoC Channel-Direction Control.......................................112 7.4.1 High-Priority FSM Operations...................113 7.4.2 Low-Priority FSM Operations....................115 7.5 Performance Evaluation.........................116 7.6 Remarks........................................120 CHAPTER 8. VC MANAGEMENT FOR BINOC...............121 8.1 Motivation.....................................121 8.2 Shared Virtual-Channel in BiNoC................125 8.3 Virtual-Channel Management in BiNoC............127 8.3.1 Resource Dependencies..........................127 8.3.2 Constrained Virtual-Channel Allocation.........129 8.4 Performance Evaluation.........................130 8.4.1 Synthetic Traffic Analysis.....................131 8.4.2 Hotspot Traffic Analysis.......................132 8.4.3 Implementation Overhead........................133 8.5 Remarks........................................134 CHAPTER 9. CONCLUDING REMARKS....................137 APPENDIX A. SIMULATION ENVIRONMENT................139 A.1 NoC Platform...................................139 A.2 Synthetic Traffic..............................139 A.3 E3S Benchmark..................................140 APPENDIX B. PERFORMANCE METRICS...................143 BIBLIOGRAPHY............................................145 | |
| dc.language.iso | en | |
| dc.subject | 晶片上網路架構 | zh_TW |
| dc.subject | on-chip interconnection network | en |
| dc.title | 一個可動態調變之晶片上網路架構設計 | zh_TW |
| dc.title | Design of a Dynamic Self-Reconfigurable on-Chip Interconnection Network | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 熊博安,張耀文,黃威,郭斯彥,周景揚,楊佳玲 | |
| dc.subject.keyword | 晶片上網路架構, | zh_TW |
| dc.subject.keyword | on-chip interconnection network, | en |
| dc.relation.page | 155 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2011-08-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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