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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉致為 | |
dc.contributor.author | Shang-Chi Yang | en |
dc.contributor.author | 楊尚輯 | zh_TW |
dc.date.accessioned | 2021-06-08T06:56:29Z | - |
dc.date.copyright | 2009-07-27 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-07-23 | |
dc.identifier.citation | chapter 2
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[7] HY Lee et al, “Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM,” IEDM Tech. Dig., p.297-300, 2008. chapter 3 [1] M. Aoiki, T. Hashimoto, T. Yamanaka and T. Nagan,“ Large 1/f noise in polysilicon TFT loads and its effects on the stability of SRAM cells,” Jpn. J. Appl. Phys. 35 (1996), p. 838. [2] A. Corradeti, R. Leoni, R. Carluccio, G. Fortunato, C. Reita, F. Plais and D. Pribat, “Evidence of carrier number fluctuation as origin of 1/f noise in polycrystalline silicon thin film transistors, ” Appl. Phys. Lett. 67 (1995), p. 1730. [3] C.F. Huang “Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors,” IEEE Electron Device Letters, vol.29, pp.1332, Dec.2008. [4] G. Ghibaudo, “On the theory of carrier number fluctuations in MOS devices,” Solid State Electron. 32 (1989), p. 563. [5] E. Simoen and C. Claeys, “On the flicker noise in submicron silicon MOSFETs,” Solid-State Electron., vol. 43, pp. 865-882, 1999. [6] C. Surya and T. Y. Hsiang, “Theory and experiment on the 1/ f’ noise in P-channel metal-oxide-semiconductor field-effect transistors at low drain bias,” Phys. Rev., vol. B33, pp. 4898-4905, 1986. [7] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A unified model for the flickernoise in metal–oxide–semiconductor field-effect transistors,”IEEE Trans. Electron Devices, vol. 37, no. 5, pp. 654–665, May 1990. [8] J. Hsu, J. Wang, J. Woo, and C. R. Viswanathan, “Flicker noise in thin-film fully-depleted SOI MOSFET’s,” in Proc. IEEE Int. SOI Conf.,1991, pp. 30–31. [9] Z. Celik-Butler and T. Y. Hsiang, “Spectral dependence of 1/fr noise on gate bias in N-MOSFET’s,” Solid-State Electron., vol. 30, pp. 419-423, 1987. [10] Z. Celik-Butler, and T. Y. Hsiang, “Spectral dependence of 1/fr noise on gate bias in N-MOSFETS,” Solid-State Electronics, vol.30, no. 4, pp. 419–423, 1987 [11] C. Y. Tsai and J. Gong, “l/f noise in linear region of lightly doped drain (LDD) MOSFET’s,” IEEE Trans. Electron Devices, vol. 35, pp.2373-2374, 1988. [12] Jalal Jommah, Francis Balestra, and Gerard Ghibaudo, “ Low Frequency noise in advanced Si Bulk and SOI MOSFET,” Journal of Telecommunications and Information technology, pp.24-33, 2005. [13] Ryo IMURA, “The World's Smallest RFID u-Chip, bringing about new business and lifestyles,” Symposium on VLSI Circuits 2004, Digest ofTechnical Papers, p.120 – 123 (2004). [14] E. Cantatore, T. C. T. Geuns, A. F. A. Gruijthuijsen, G. H. Gelinck,S. Drews, and D. M. de Leeuw, “A 13.56 MHz RFID system based on organic transponders,” in IEEE ISSCC Dig. Tech. Papers, 2006, pp.272–273. chapter 4 [1] M. Jo, C.-G. Lim, and E. W. Zimmers, “RFID tag detection on a water content using a back-propagation learning machine,” KSII Trans. Internetand Inf. Syst., vol. 1, no. 1, pp. 19–32, Dec. 2007. [2] J. N. Burghartz, D. C. Edelstein, M. Soyuer, H. A. Ainspan, and K. A.Jenkins, “RF circuit design aspects of spiral inductors on silicon,” IEEEJ. Solid-State Circuits, vol. 33, pp. 2028–2034, Dec. 1998. [3] Jun-Bo Yoon, Chul-Hi Han, Euisik Yoon, and Choong-Ki Kim, “Monolithic High-Q Overhang Inductors Fabricated on Silicon and Glass Substrates,” in IEDM Tech. Dig., 1999, pp. 753–756. [4] M. El Kaamouchi, P. Delatte, M. Si Moussa, J.-P. Raskin, D. Vanhoenacker-Janvier, “Temperature behavior of spiral inductors on high resistivity substrate in SOI CMOS technology” Solid-State Electronics 52 (2008) Pages 1915-1923. chapter 5 [1] Louis L., Bucciarrelli, Jr, “Power Loss in Photovoltaic Arrays due to Mismatch in Cell Characteristics,” Solar Energy 23 (1979), pp. 277–288. [2] CHARLES E. CHAMBERLIN, PETER LEHMAN, JAMES ZOELLICK, and GHAN PAULETTO, “Effect of Mismatch Losses in photovoltaic Arrays,” Solar Energy 54 (1995), pp. 165–171. [3] N.D. Kaushika, Anil K. Rai, “An Investigation of Mismatch Losses in Solar Photovoltaic Cell Networks,” Solar Energy 32 (2007), pp. 755–759. [4] Achim Woyte, Johan Nijs and Ronnie Belmans, “Partial shadowing of photovoltaic arrays with different system configurations: literature review and field test results,” Solar Energy 74 (2003), pp. 217–233. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25871 | - |
dc.description.abstract | 在本論文中,第一部分為電阻式記憶體 (RRAM) SPICE 模型的建立。RRAM屬於非揮發性記憶體中的一種,利用外加電壓可在高電阻態 (high resistance state, HRS) 與低電阻態 (low resistance state, LRS) 間切換以記錄邏輯1與0,此種記憶體具有低操作電壓與功率 (寫入電壓 < 3 V, 讀取電壓 ~ 0.1 V)、高度微縮性 (結構簡單,為兩層金屬電極夾二元過鍍金屬氧化物)、可多階操作 (可大幅提升記憶體密度)、超快讀取與寫入速度 (< 10 ns)、高耐用度 (> 10 年)、可靠之資料保存能力等優勢,其與相變化記憶體 (phase change memory, PCM) 同為次世代非揮發性記憶體中的主要競爭者。對產業界而言,積體電路量產之前必須對電路進行模擬驗證,以確保成功,因此,本論文將利用業界普遍採用之HSPICE模擬軟體建立RRAM之SPICE電路模型,對現今動輒數百萬記憶體單元之記憶體產品而言,簡易之SPICE電路模型可大幅提升模擬效率。第二部份對薄膜電晶體的雜訊做理論上的分析並對實驗結果提出一個的簡單物理模型,且利用Eldo模擬軟體建立SPICE 模型,作為電路設計時模擬用。並使用TFT製程模擬RFID tag.第三部份為在玻璃基板上製作螺旋電感,第四部份為分析太陽能電池模組效率衰退與元件均勻度的關係。 | zh_TW |
dc.description.abstract | In this thesis, the first part is developing the Resistive random access memory SPICE model. Resistive random access memory (RRAM) is one of the many types of nonvolatile memory, which utilizes the switching between high resistance state (HRS) and low resistance state (LRS) by the applied voltage to record logic 1 and logic 0. The RRAM boasts of low operating voltage and low power (program voltage < 2 V, read voltage ~ 0.1 V), good scalability (because of its simple structure, which is usually a binary transition-metal oxide sandwiched by two metal electrodes), multilevel cell (MLC) operation (strongly boost the density of memory), ultra-fast read and program speed (< 10 ns), high endurance (> 10 years), and reliable data retention time. The RRAM, as well as phase change random access memory (PCRAM), are main competitors in next-generation nonvolatile memory. To the industrial sector, it is imperative to verify the circuit design before mass-producing the integrated circuit products, which ensures the success of the tapeout. Therefore, we will use commercial HSPICE software to develop an RRAM SPICE circuit model. A compact SPICE model will greatly enhance the simulation speed of today’s memory product composed of several millions unit cells.
The second part is the physical analysis of low frequency of thin film transistors. We propose a simple physical model to explain the experimented results and develop a spice model with Eldo applying to circuit simulation. In addition, gives a simple RFID tag simulation using TFT process. The third part is about the spiral inductors fabricated on glass substrate. Finally, we analyze the efficiency degradation of solar cell modules due to cell non-uniformity distribution. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T06:56:29Z (GMT). No. of bitstreams: 1 ntu-98-R96943058-1.pdf: 2766300 bytes, checksum: 379c7f864a25d70dd2a2f3a7a43e1563 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | List of Tables VIII
List of Figures IX Chapter 1 Introduction 1.1 Motivation 1 1.2 Dissertation Organization 2 Chapter 2 Resistive RAM Spice Macro Model 2.1 Introduction 4 2.1.1 Classification of Resistance Switching Behavior 5 2.1.2 Resistive Switching Mechanisms 7 2.2 Development of Macromodel of Single-Bit RRAM 8 2.2.1 HfO2 Based RRAM cell 8 2.2.2 Macromodel of Single Bit RRAM 11 2.2.3 Schematic of the RRAM Macromodel 13 2.2.4 Forming Equivalent Circuit 16 2.2.5 Single-Bit Model Verification 17 2.3 Development of Macromodel of Multi-Bit RRAM 21 2.3.1 Multi-Level for RSET 21 2.3.2 Multi-Level for RRESET 24 2.4 Transient Simulation under Various Conditions 26 2.4.1 Multi-level Operation for 3 stages RRESET 26 2.4.2 Initial State Condition & Forming Verification 28 2.5 Co-simulation with Simple Read/Write Circuit 31 2.6 Summary and Conclusion 36 Reference 37 Chapter 3 Low Frequency Noise Analysis of Thin Film Transistor and Application of Radio Frequency Identification 3.1 Introduction 38 3.1.1 Device Fabrication of LTPS Thin Film Transistors 39 3.1.2 Low Frequency Noise Model in TFTs 39 3.2 Analysis of Frequency Exponent in McWhorter Model 41 3.2.1 McWhorter Theory 41 3.2.2 Noise Spectral at Varying Gate Bias under Linear Region 43 3.2.3 Discussion and Model 45 3.3 Analysis of Flick Noise with Correlated Mobility Fluctuation Model 50 3.3.1 Analysis the Sign of Colombo Scattering Parameter 50 3.4 Noise performance of Lightly Doped Drain 53 3.4.1 Impact of Series Resistance 53 3.5 Radio Frequency Identification 57 3.5.1 Transit Frequency 57 3.5.2 Corner Frequency 59 3.5.3 l/f Noise Spice Modeling in Sat. Region using Eldo simulator 60 3.6 Summary and Conclusion 69 Reference 70 Chapter 4 Inductors fabricated on poly-silicon and glass substrate 4.1 Introduction 72 4.2 On-Chip Spiral Inductor Model 73 4.3 Parameter Extraction Methodology 74 4.4 Extraction Results and Discussion 76 4.5 Verification of Inductor Behavior Model 78 4.6 Summary and Conclusion 81 Reference 82 Chapter 5 Statistics Analysis of Efficiency Degradation of Solar Cell Array due to Uniformity Issue 5.1 Introduction 83 5.2 Mismatch Losses in Solar Cell Arrays 83 5.3 Analysis of Solar Cell Maximum Efficiency 84 5.3.1 One Diode Solar Cell Model 84 5.3.2 Influence of Model Parameters to Efficiency 85 5.4 Influence on Solar Model Parameters on Maximum Efficiency of Solar Cell Connected in Parallel 90 5.4.1 Analysis Condition and Simulation Results 90 5.5 Influence of Solar Cell Model Parameters on Maximum Efficiency of Solar Cell Connected in Series 93 5.6 Summary and Conclusion 94 Reference 96 Chapter 6 Summary and Future work 6.1 Summary 97 6.2 Future work 98 | |
dc.language.iso | en | |
dc.title | 電阻式記憶體SPICE模型製作與薄膜電晶體雜訊
及太陽能電池效率分析 | zh_TW |
dc.title | Development of Resistive Random Access Memory
SPICE Model and Analysis of Thin Film Transistor Noise and Solar Cell Efficiency | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 蔡銘進,汪大暉,陳其賢(Chi-Shian Chen) | |
dc.subject.keyword | 電阻式記憶體,相變化記憶體,薄膜電晶體,螺旋電感,太陽能電池, | zh_TW |
dc.subject.keyword | resistive random access memory,phase change memory,TFT,spiral inductors,solar cell, | en |
dc.relation.page | 99 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2009-07-24 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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