可適性接收機與次諧波注入鎖相迴路分析與設計

Abstract

這篇論文的主題主要分為三個部分，第一個部分是針對資料時脈回覆電路之擾動容忍轉移函數做一個內建自我測試電路，此電路運用了隨機二進制序列及多模除頻器去產生帶有擾動的資料，而正弦抖動所需之三角積分調變器則由FPGA板所產生，無需使用額外昂貴的量測儀器。此自我校正電路所測得之擾動容忍轉移函數之方均根誤差為 <13%。 第二部分實做了一個高速有線接收機，此接收機提出了創新的可適性無限脈衝決策回授等化器去補償通道損耗，在32.7dB通道損耗的情況下，此接收機仍可以回復資料和時脈。此外，我們提出了一個頻率偵測器和鎖定偵測器。就算在高損耗的環境下，此頻率偵測器仍然可以使資料時脈回覆電路鎖頻。 第三部分我們實現了一個低相位雜訊鎖相迴路。我們使用了次諧波注入之技巧去壓抑震盪器之相位雜訊。此外，我們提出了一個注入時間點校正之技巧去對齊震盪器之最佳注入點，使得此次諧波鎖相迴路系統可以穩定。量測到的相位雜訊可以從原本的-113dBc/Hz降低至-132dBc/Hz在1MHz之頻率偏移，而方均根抖動可以從原本的362fs改善至170fs。

This thesis consists of three parts. The first part aims to design a jitter-tolerance self-test technique for CDR circuit. PRBS and dual-modulus divider is employed to generate the data with sin wave jitter. The required sigma-delta modulator is generated by FPGA board, so expensive equipments are not needed. The measured RMS error of jitter-tolerance transfer curve by BIST circuit is smaller than 13%. The second part implements a high-speed wireline receiver. We proposed an innovative adaptive DFE-IIR approach to compensate channel loss. Under 32.7dB channel loss, this receiver is still able to recover data and clock. Besides, we propose a FD and LD. Even though in high loss environment, the FD and LD are able to help CDR to lock frequency. The third part introduces a low phase noise PLL. Subharmonically injection-locked technique is employed to suppress VCO accumulation noise. Besides, we propose a injection timing calibration technique to align the injection pulse with optimal injection point, which ensures subharmonically injection-locked PLL stable. The measured phase noise is improved from -113dBc/Hz to -132dBc/Hz at 1MHz offset. The RMS jitter can be improved from 362fs to 170fs.