應用於寬頻接收機之CMOS高速關鍵零組件

Abstract

莫爾定律的趨勢引領了CMOS技術朝向寬頻通訊系統, 其中包括有高資料率無線通訊(ISI/mm-Wave band and Radar)和高覆載有線通訊(SONET/SDH, Fiber Channel, and Gigabit Ethernet). 為實現Gb/s寬頻接收機, 前端電路和時脈產生器皆扮演關鍵角色之一. 在此篇論文, 提出了應用於寬頻接收機之CMOS高速關鍵零組件. 雖然III-V或Bipolor製程已經廣泛使用在40GB/s與60GHz接收機, 但是他們有著大量的功率消耗, 以及在搭配數位後端整合上的困難. CMOS技術則具有高整合還有低功率低成本優勢. 然而CMOS有些缺陷問題, 譬如: 有限截止頻率, 通道長度調變, 閘極漏電, 米勒效應, 繞線寄生電容, 基版損耗, 有限電壓等等. 為解決以上問題, 數項高速技術被提出, 分析與驗證. 首先, 介紹一應用於有線通訊的35-Gb/s 0.13um CMOS限幅放大器. 它採用串接式分布放大器, 主動回授架構, 和晶片變壓器元件, 可延展增益頻寬積達到5.2倍之多. 輸入偏壓移除級和輸出寬頻緩衝級也被提出來改善靈敏度和增大振幅. 第二, 說明一應用於毫微米波通訊的60GHz 90nm CMOS 頻率合成器. 為了符合無線應用上有限通道頻寬, 它需要低的參考頻率, 因此破壞參考突波, 穩定時間和相位雜訊上的表現. 藉由提出的諧波鎖定技術, 除頻訊號會鎖在參考頻率的m倍. 頻帶內起因於相位偵測器和除頻器的雜訊會被衰減 , 而不會有任何迴路頻寬的賠償. 相對於PFD形式的頻率合成器, 此提出的技術可減少57%的穩定時間. 最後, 提出一57-77GHz 90nm CMOS 毫微米波超寬頻接機. 為了高速時脈產生器, 提出的整合式邏輯多工除頻器勢必需要. 然後, 藉著雙降頻方法, 只要一個時脈產生器即可達成60GHz/77GHz雙頻帶應用. 為此目的, 分別提出不同架構時脈產生器, 例如四倍諧波鎖定相位鎖定器, 量化雜訊位移式小數型頻率合成器. 以上關鍵電路大大促進CMOS寬頻電路的可實現性與可靠度.

Moore’s law has driven CMOS technologies toward broadband communication systems, which contains high-data-rate wireless communications (ISI/mm-Wave band and Radar), and high-capacity wireline communications (SONET/SDH, Fiber Channel, and Gigabit Ethernet). To realize Gb/s broadband transceivers, both front-end and clock generator play one of the critical roles. In this dissertation, CMOS high-speed analog key components for broadband receivers are presented. Even though III-V or bipolar processes had been widely used in 40Gb/s and 60GHz transceivers, they may have a large amount of power dissipation and make it difficult to fully integrate with the digital back-end. CMOS technology is to allow high levels of integration as well as low power and low cost. However, there are several problems in lossy CMOS, such as limited cut-off frequency fT, channel-length modulation, gate leakage, Miller effect, routing parasitic capacitance, substrate loss, limited supply voltage, etc. To resolve the above problems, several high-speed techniques are proposed, analyzed, and verified. First, a 35-Gb/s limiting amplifier (LA) in 0.13um CMOS is presented for wireline communications. It incorporates the cascaded distributed amplifier (CDA) with active-feedback and on-chip transformers to extend the gain-bandwidth product of active-feedback resistively-loaded amplifier by a factor of 5.2. The input offset-canceling stage and output broadband buffer are also described to improve the sensitivity and enlarge the amplitude. Second, a 60GHz frequency synthesizer in 90nm CMOS is presented for mm-wave communications. To accommodate the limited channel space for wireless applications, it requires a low reference frequency, therefore corrupting the performance of reference spur, settling time, and phase noise. Based on the proposed harmonic-locked technique, the divided frequency fdiv will lock with m times the frequency of fref. Resulting from the phase detector and dividers, in-band noise is attenuated by a factor of without the penalty of loop bandwidth. Compared with the PFD-type synthesizer, the proposed technique achieves a 57% reduction in settling time. Finally, a 57-77GHz mm-wave UWB receiver in 90nm CMOS is presented. To have a high-frequency clock generator, the proposed prescaler using merged-logic topology is needed. By using dual down-conversion approach, only one clock generator is needed to attain 60GHz/77GHz applications. For this purpose, the clock generator is proposed using different architectures: a quadruplicate-locked PLL and a ΔΣ fraction-N frequency synthesizer with the quantization noise shifting technique. The above key components facilitate the CMOS broadband realizations.