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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎 | |
| dc.contributor.author | Chen-Wei Lin | en |
| dc.contributor.author | 林政偉 | zh_TW |
| dc.date.accessioned | 2021-06-08T06:07:04Z | - |
| dc.date.copyright | 2007-07-23 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-07-19 | |
| dc.identifier.citation | [1] Y. M. Liu, M. Miller, F. Henley, M. Nguyen, J. Levine, and H. Steemers. Line Open and Short Defect Classification Methodology for AMLCD Array Test Using Voltage Imaging. SID Symposium Digest of Technical Papers, 1995.
[2] S. L. Wright, K. W. Warren, P. M. Alt, R. R. Horton, C. Narayan, P. F. Greier, and M. Kodate. Active Line Repair for Thin-Film-Transistor Liquid Crystal Displays. IBM Journal of Research and Development, VOL. 42 NO. 3/4 MAY/JULY, 1998. [3] L. C. Jenkins, R. J. Polastre, R. R. Troutman, and R. L. Wisnieff. Functional Testing of TFT/LCD Arrays. IBM Journal of Research and Development, VOL. 36 NO. 1 JANUARY, 1992. [4] Y. C. Lin and H. D. Shieh. In-Process Functional Testing of Pixel Circuit in AM-OLEDs. IEEE Transactions on Electron Devices, Volume 52, Issue 10, Oct. 2005. [5] J. C. Hunter, M. Brunner, R. Schmid, and F. Abboud. Issues and Challenges Associated with Electrical Testing of Large LCD-TV Arrays. SID Symposium Digest of Technical Papers, Volume 36, Issue 1, pp. 1800-1803 May, 2005. [6] S. L. Wright and R. Nywening. A Transmission-Line Approach for Line-Continuity Testing of Active-Matrix Arrays. SID Symposium Digest of Technical Papers, 1995. [7] M. Kodate, F. R. Libsch, T. Iwami, L. Jenkins, M. Mastro, Y. Mekata, R. Polastre, and T. Taguchi. Next Generation TFT-Array Testing for High Resolution/High Content AMLCDs. SID Symposium Digest of Technical Papers, Volume 30, Issue 1, pp. 72-75 May, 1999. [8] T. Nagano, H. Kageyama, H. Akimoto, Y. Mikami, and H. Sato. A 5-Inch SVGA Low-Temperature Poly-Si TFT-LCD with Integrated Digital Interface Driver. In International Conference on Solid-State and Integrated-Circuit Technology, Volume 2, 22-25 Oct. 2001. [9] T. Nakamura, M. Karube, H. Hayashi, K. Nakamura, N. Tada, H. Fujiwara, J. Tsutsumi, and T. Motai. Low-Temperature Poly-Si TFT-LCD with an Integrated Analog Circuit. Journal of the Society for Information Display, Volume 10, Issue 3, pp. 203-207 September, 2002. [10] Y. S. Yoo, J. Y. Choi, H. S. Shim, and O. K. Kwon. A High Accurate Analog Buffer Circuit using Low Temperature Poly-Si TFT. SID Symposium Digest of Technical Papers, Volume 35, Issue 1, pp. 1460-1463 May, 2004. [11] C. W. Lin, T. K. Chang, C. K. Jan, M. H. Hsieh, C. Y. Tsai, S. C. Chang, and Y. M. Tsai. LTPS Circuit Integration for System-on-Glass LCDs. Journal of the Society for Information Display, Volume 14, Issue 4, pp. 353-362 April, 2006. [12] Y. Dai. Design and Operation of TFT Panels. Wu-Nan Culture Enterprise. [13] A. Nathan, G. R. Chaji, and S. J. Ashtiani. Driving Schemes for a-Si and LTPS AMOLED Displays. Journal of Display Technology, VOL. 1, NO. 2, DECEMBER 2005. [14] S. H. Jung, H. S. Shin, J. H. Lee, and M. K. Han. An AMOLED Pixel for the VT Compensation of TFT and a p-Type LTPS Shift Register by Employing 1 Phase Clock Signal. SID Symposium Digest of Technical Papers, Volume 36, Issue 1, pp. 300-303 May, 2005. [15] G. R. Chaji, D. Striakhilev, and A. Nathan. A novel a-Si:H AMOLED Pixel Circuit Based on Short-Term Stress Stability of a-Si:H TFTs. IEEE Electron Device Letters, Volume 26, Issue 10, Oct. 2005. [16] M. D. Ker, C. K. Deng, and J. L. Huang. On-Panel Output Buffer with Offset Compensation Technique for Data Driver in LTPS Technology. Journal of Display Technology, VOL. 2, NO. 2, JUNE 2006. [17] S. S. Kim, High-Aperture-Ratio and Fault-Tolerant TFT-LCDs Using a-Si:H TFTs, SID International Symposium Digest, 1996. [18] S. S. Kim, S. H. Moon, D. G. Kim, and N. D. Kim, High-Aperture and Fault-Tolerant Pixel Structure for TFT-LCDs, SID International Symposium Digest, pp. 15-18, 1995. [19] D. Freeman, and J. Hawthorne, Implications of Super High Resolution to Array Testing, SID International Symposium Digest, Volume 31, Issue 1, pp. 375-377 May, 2000. [20] A. Laknaur and H. Wang. Built-In-Self-Testing Techniques for Programmable Capacitor Arrays. International Symposium on Quality of Electronic Design, Page(s): 434-439, 21-23 March, 2005. [21] S. R. Durbha, A. Laknaur, and H. Wang. Investigating the Efficiency of Integrator-Based Capacitor Array Testing Techniques. VLSI Test Symposium, Page(s): 6pp, 30 April - 4 May, 2006. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25265 | - |
| dc.description.abstract | 薄膜電晶體陣列是一種擁有數千至數百萬個圖素之矩陣結構的電路。若是需要測試所有在陣列上的圖素與傳輸線是否有製造上的缺陷，這將是一件相當困難的工作。因此，傳統上都必須使用大量的探測埠與相當長的測試時間以致於達到夠高之測試的準度。為了改善此情形，在這篇論文中提出了兩個分別針對圖素儲存電荷和掃描線斷裂之內建式自我測試技術。所提出之技術都可被應用在SoG (System on Glass)製造概念。 | zh_TW |
| dc.description.abstract | TFT array is a matrix-like structure which contains thousands to millions pixels to display information. However to it’s difficult to make sure that the TFT panel manufactured is no-defect which means all the pixels are well and all the metal wires are continuous. Therefore it’s necessary to test the array including the wires and the pixels. For testing the TFT array, large probes number of ATE and long testing time are needed traditionally. To improve this, this thesis proposed two built-in self-test techniques for testing the pixels and the scan/data line respectively. Both the technique can also be applied into SoG (System on Glass) concept. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T06:07:04Z (GMT). No. of bitstreams: 1 ntu-96-R94943164-1.pdf: 952660 bytes, checksum: 5bdd15477eb7e4e2309806d2b5534049 (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | Abstract...........................................................................................................................i
Chapter 1 Introduction...................................................................................................1 1.1 Motivation......................................................................................................1 1.2 Short summary of proposed methods.............................................................3 Chapter 2 Preliminaries..................................................................................................4 2.1 TFT Array Driving Circuitry..........................................................................4 2.1.1 The Scan Driver..................................................................................4 2.1.2 The Data Driver...................................................................................7 2.2 TFT Array Testing.......................................................................................10 2.2.1 Common TFT Array Defects............................................................10 2.2.2 TFT Array Manufacturing Testing Techniques................................12 2.2.3 TFT Array Design-for-Test Techniques.............................................14 2.3 System-on-Glass Design and Test Challenges.............................................16 Chapter 3 A Charge Sensing Technique for TFT Array Testing...................................18 3.1 Overview......................................................................................................18 3.2 The Charge Sensing and Serial Readout Process.........................................20 3.2.1 The Pixel Model...........................................................................20 3.2.2 Functional mode...........................................................................21 3.2.3 Charge Sensing Mode..................................................................22 3.2.4 The serial readout mode...............................................................28 3.2.5 The charge sensing test flow.........................................................30 3.3 Control signal generation.............................................................................32 3.4 Practical issues.............................................................................................33 3.5 Simulation results.........................................................................................34 Chapter 4 A Testing & Repairing Technique for Open Scan Line Defect....................38 4.1 The scan line self-testing and repair scheme................................................38 4.1.1 Scan Line Testing..............................................................................40 4.1.2 Scan Line Repair...............................................................................43 4.2 a-Si Circuit Design.......................................................................................45 4.2.1 Conventional active load inverter......................................................45 4.2.2 The three-stage inverter with positive feedback................................46 4.2.3 One-stage inverter with auto-on/off active load................................48 Chapter 5 Conclusion & Future Work..........................................................................51 5.1 Conclusion....................................................................................................51 5.2 Future work..................................................................................................51 References....................................................................................................................52 | |
| dc.language.iso | en | |
| dc.subject | 薄膜電晶體陣列 | zh_TW |
| dc.subject | 內建式自我測試 | zh_TW |
| dc.subject | 電荷感測 | zh_TW |
| dc.subject | 內建式自我修復 | zh_TW |
| dc.subject | built-in self-repair | en |
| dc.subject | TFT array | en |
| dc.subject | built-in self-test | en |
| dc.subject | charge sensing | en |
| dc.title | 適用於薄膜電晶體顯示陣列之自我測試與自我修復技術 | zh_TW |
| dc.title | Built-In Self-Test and Self-Repair Techniques for TFT Array | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 呂良鴻,李泰成 | |
| dc.subject.keyword | 薄膜電晶體陣列,內建式自我測試,電荷感測,內建式自我修復, | zh_TW |
| dc.subject.keyword | TFT array,built-in self-test,charge sensing,built-in self-repair, | en |
| dc.relation.page | 53 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2007-07-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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