轉角不連續結構之電氣特性分析與補償設計

Abstract

當資料傳輸速率到達數個十億位元的範圍以上，在印刷電路板上由於轉角所造成的不連續效應將不能再被忽略。本論文利用商用全波模擬軟體得到不連續結構處的Z 參數矩陣，且建立起單根轉角的T-型等效電路，並加以驗證無誤後，便可快速且準確地分析此一不連續結構在高速數位電路中對信號完整度所產生的影響。 由於差模信號具備有低雜訊產生及高共模雜訊抑制的能力，因此在具有數十億位元的數位產品上被廣泛地應用。而在高速數位電路設計上，常用以降低共模雜訊的差模轉角佈線結構，如背對背雙轉角，本論文將探討與分析其於時域下的信號完整度。而一種新穎的蜿蜒型延遲線將被提出，以強化信號完整度之設計需求。然而本篇論文最重要的貢獻是提供完整的蜿蜒型延遲線之設計流程，以期能 讓設計者有一完整的準則可以遵循並且可以設計出理想且實用的蜿蜒型延遲線。 最後，也透過模擬與實驗結果的一致性，驗證了轉角加上所提出之蜿蜒型延遲線的可行性。

As the data rates increase into the multi-gigabit range, the effect of bend discontinuities on printed circuit board becomes non-negligible. this paper utilizes the commercial electromagnetic field solver to extract Z-parameters of the bend discontinuities. With the T-type equivalent circuit being extracted and verified, the waveform along bent transmission line in a high-speed digital circuit is simulated to demonstrate the signal integrity effect of the single bend. Because the differential signaling has the property of low noise generation and the high immunity to common-mode noise, it has become a popular option for multi-gigabit digital applications. The signal integrity analyses for bent differential transmission lines in a high-speed digital circuit are therefore performed in the time domain. One practical compensation scheme, the dual back-to-back bends, for the common-mode noise reduction are further investigated. To alleviate the common-mode noise at the receiver, a novel compensation scheme in use of the bump delay line is also proposed. However, the most important contribution in this thesis is to provide the complete flows of designing bump delay lines so that the designer could follow the steps of the proposed method to design a perfect and practical bump while both keeping good SI and using least layout space. Finally, the comparison between the simulation and measured results validates the analysis approach of differential bends with the proposed bump delay lines.