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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
dc.contributor.author | Cheng-Yu Chang | en |
dc.contributor.author | 張呈毓 | zh_TW |
dc.date.accessioned | 2021-06-08T06:01:29Z | - |
dc.date.copyright | 2007-07-31 | |
dc.date.issued | 2007 | |
dc.date.submitted | 2007-07-29 | |
dc.identifier.citation | [1] Serial ATA Workgroup, “Serial ATA Revision 2.6,” Revision 0.50 1-Aug 2006
[2] K.B. Hardin, J.T. Fessler, and D.R. Bush, “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions,” IEEE International Symposium on Electromagnetic Compatibility, pp. 227–231, Aug. 1994. [3] H.S. Li, Y.C. Cheng, and D. Puar, “Dual-Loop Spread-Spectrum Clock Generator,” IEEE International Solid-State Circuits Conference, pp. 184-185, Feb. 1999. [4] H.H. Chang, I.H. Hua, and S.I. Liu, ”A Spread-Spectrum Clock Generator with Triangular Modulation,” IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 673-676, Apr. 2003. [5] H.W. Chen and J.C. Wu, “A Spread Spectrum Clock Generator for EMI Reduction,” IEICE Trans. Electron., vol. E84-C, no. 12, pp. 1959-1966, Dec. 2001. [6] Y. Moon, D.K. Jeong, and G. Kim, “Clock Dithering for Electromag Netic Compliance Using Spread-Spectrum Phase Modulation,” IEEE International Solid-State Circuits Conference, pp. 186–187, Feb. 1999. [7] M. Aoyama, K. Ogasawara, M. Sugawara, T. Ishibashi, S. Shimoyama, K. Yamaguchi, and T. Yanagita, “3Gbps, 5000ppm Spread Spectrum SerDes PHY with Frequency Tracking Phase Interpolator for Serial ATA,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 107-110, Jun. 2003. [8] J.Y. Michel and C. Neron, “A Frequency Modulated PLL for EMI Reduction in Embedded Application,” IEEE International ASIC/SOC Conference, pp. 362–365, Sep. 1999. [9] W.T. Chen, J.C. Hsu, H.W. Lune, and C.C. Su, “A Spread Spectrum Clock Generator for SATA-II,” IEEE International Symposium on Circuits and Systems, pp. 2643-2646, May. 2005. [10] M. Kokubo, etc, “Spread-Spectrum Clock Generator for Serial ATA using Fractional PLL Controlled by ΔΣ Modulator with Level Shifter,” IEEE International Solid-State Circuits Conference, pp. 160-590, Feb. 2005. [11] M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, M. Suzuki, T. Hayasaka, T. Takahashi, and J. Kasai, “Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit ΣΔ Modulator-Controlled Fractional PLL,” IEICE Trans. Electron., vol. E89–C, no. 11, pp. 1682-1688, Nov. 2006. [12] Y.B. Hsieh and Y.H. Kao, “A Spread-Spectrum Clock Generator Using Fractional-N PLL with an Extended Range Σ∆ Modulator,” IEICE Trans. Electron., vol. E89–C, no. 6, pp. 851-857, Jun. 2006. [13] http://www.altera.com.cn/support/devices/pll_clock/jitter/pll-jitter.html [14] B. Razavi, RF Microelectronics, Pretice-Hall, Inc., 1998. [15] F.M. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. Communications, vol. 28, no. 11, pp. 1849-1858, Nov. 1980. [16] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill international editions, 2001. [17] B. De Muer and M.S.J. Steyaert, “A CMOS Monolithic ΔΣ-Controlled Fractional-N Frequency Synthesizer for DCS-1800,” IEEE Journal of Solid-State Circuits, vol. 37, no. 7, pp. 835 – 844, Jul. 2002. [18] W. Rhee, B.S. Song, and A. Ali, “A 1.1-GHz CMOS Fractional-N Frequency Synthesizer with a 3-b Third-Order ΔΣ Modulator,” IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1453-1460, Oct. 2000. [19] T.A.D. Riley, M.A. Copeland, and T.A. Kwasniewski, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553-559, May. 1993. [20] B. Miller and B. Conley, “A Multiple Modulator Fractional Divider,” Symposium on Frequency Control, pp. 559-568, May. 1990. [21] D. Ham and A. Hajimiri, “Concepts and Methods in Optimization of Integrated,” IEEE Journal of Solid-State Circuits, vol. 36, no. 6, pp. 896-909, Jun. 2001. [22] D.B. Lesson, “A Simple Model of Feedback Oscillator Noise Spectrum,” Proceedings of the IEEE, pp. 329-330, Feb. 1966. [23] T.K.K. Tsang and M.N. El-Gamal, “A High Figure of Merit and Area-Efficient Low-Voltage (0.7-1V) 12GHz CMOS VCO,” IEEE Radio Frequency Integrated Circuits, pp. 89-92, Jun. 2003. [24] A.H. Mostafa and M.N. El-Gamal, “A CMOS VCO Architecture Suitable for Sub-1 Volt High-Frequency (8.7-10 GHz) RF Applications,” International Symposium on Low Power Electronics and Design, pp. 247-250, Aug. 2001. [25] M. Tiebout, H.D. Wohlmuth, and W. Simburger, “A 1V 51GHz Fully-Integrated VCO in 0.12/spl mu/m CMOS,” IEEE International Solid-State Circuits Conference, pp. 238-239, Feb. 2002. [26] J.G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996. [27] A. Shinmyo, M. Hashimoto, and H. Onodera, “Design and Optimization of CMOS Current Mode Logic Dividers,” IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp. 434-435, Aug. 2004. [28] D. Theil and C. Durdodt, “A Fully Integrated CMOS Frequency Synthesizer for Bluetooth,” IEEE Radio Frequency Integrated Circuits, pp. 103-106, May, 2001. [29] J. Yuan and C. Svensson, “High-speed CMOS Circuit Technique,” IEEE Journal of Solid-State Circuits, vol. 24, no. 1, pp. 62-70, Feb. 1989. [30] W.O. Keese, “An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump Phase-Locked Loops,” National Semiconductor Application Note, no. 1001, May 1996. [31] 楊子震, “Design and Implementation of Spread Spectrum Clock Generators,” Master Thesis, National Taiwan University Graduate Institute of Electronics Engineering, 2004. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25067 | - |
dc.description.abstract | EMI (Electro-Magnetic Interference) causes more destruction to the transmitting signal since the operating frequency is higher than before. Spread spectrum clocking (SSC) is a method that can reduce the EMI effectively. This method is more and more popular since it is easy to design and suitable for integrated IC. Serial ATA is a high speed external mass storage device having the SSC specifications as following: a triangular modulation profile with down spread, a 5000 ppm frequency deviation, a 30~33KHz modulation frequency, an EMI reduction larger than 7dB, and a 3ps RMS jitter @ 250 cycles.
Our research is stressed on low-jitter design. Due to the higher operating frequency requirement, design with low-jitter performance becomes more and more important and thus more difficult to realize. VCO phase noise dominates the jitter performance of PLLs. Therefore, we proposed a LC tank VCO with low phase noise characteristic. The simulation results show that the phase noise is -119.8dBc/Hz @1MHz offset voltage and FoM is -190.8. In this Thesis, a spread spectrum clock generator (SSCG) modulated by a divider is presented. The PLL is fabricated in a 0.18μm CMOS process and the whole SSCG system is integrated and tested on an FPGA board. The simulation results show that all specifications of the Serial ATA have been achieved in our system and the jitter measurement shows that the RMS jitter is 0.4ps @ 250 cycles. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T06:01:29Z (GMT). No. of bitstreams: 1 ntu-96-J94921025-1.pdf: 1083905 bytes, checksum: d4bfa11f6f09d410529fb0f24aae94cc (MD5) Previous issue date: 2007 | en |
dc.description.tableofcontents | TABLE OF CONTENTS
ABSTRACT i LIST OF FIGURES v LIST OF TABLES ix CHAPTER 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Thesis Organization 2 CHAPTER 2 BASIC OF SPREAD SPECTRUM CLOCKING 5 2.1 Specification of Serial ATA for SSC 5 2.2 Fundamental Theory of SSC 6 2.3 Types of SSC Implementation 8 2.4 Jitter Performance 10 CHAPTER 3 FRACTIONAL-N PLL USING Δ-Σ MODULATOR 13 3.1 Principle of Phase-Locked Loop 13 3.2 Analysis of Phase-Locked Loop 14 3.2.1 Voltage Controlled Oscillator 14 3.2.2 PFD with Charge Pump and Loop Filter 15 3.2.3 Linear Model of PLL 17 3.2.4 Phase Noise in PLL 19 3.3 Fractional-N Frequency Synthesis 21 3.3.1 Pulse Swallow 22 3.3.2 Fractional Spurs 24 3.4 Δ-Σ Modulator 26 3.5 Third-Order MASH Δ-Σ Modulator 29 CHAPTER 4 DESIGN OF SPREAD SPECTRUM CLOCK GENERATOR 33 4.1 System Architecture 33 4.2 Voltage Controlled Oscillator 34 4.2.1 LC-VCO Versus Ring-VCO 35 4.2.2 VCO Phase Noise 35 4.2.3 LC-VCO Technique 37 4.2.4 A New LC-VCO with Back-Gate Tuning Technique 39 4.3 Phase/Frequency Detector 40 4.4 Charge Pump 41 4.5 Programmable Charge Pump 43 4.6 Multi-Modulus Divider 44 4.7 Loop Filter 45 4.8 MASH 1-1-1 Δ-Σ Modulator 49 4.9 Triangular Generator 52 CHAPTER 5 SIMULATION RESULTS OF SPREAD SPECTRUM CLOCK GENERATOR 55 5.1 SSCG Behavior Simulation 55 5.2 Circuit Level Simulation 58 5.2.1 Voltage Controlled Oscillator 59 5.2.2 Phase/Frequency Detector and Charge Pump 62 5.2.3 Prescaler 64 5.2.4 Multi-Modulus Divider 64 5.2.5 Closed-Loop Simulation of PLL 65 5.2.6 PLL Implementation 67 5.3 MASH 1-1-1 and Triangular Generator 69 5.4 Closed-Loop Simulation of SSCG 71 CHAPTER 6 CONCLUSION 75 REFERENCE 77 | |
dc.language.iso | en | |
dc.title | 應用於Serial-ATA之6GHz低相位抖動展頻時脈產生器之設計與實作 | zh_TW |
dc.title | Design and Implementation of a Low-Jitter 6GHz Spread Spectrum Clock Generator
for Serial-ATA | en |
dc.type | Thesis | |
dc.date.schoolyear | 95-2 | |
dc.description.degree | 碩士 | |
dc.contributor.coadvisor | 張棋(Chi Chang) | |
dc.contributor.oralexamcommittee | 李泰成,林宗賢,游竹 | |
dc.subject.keyword | 展頻時脈,展頻時脈產生器,鎖相迴路,除小數式,三角積分調變器,電磁干擾,相位抖動,小數突波,壓控振盪器, | zh_TW |
dc.subject.keyword | SSC,SSCG,Serial ATA,PLL,Fractional-N,Δ-Σ modulator,EMI,Jitter,Fractional spurs,Voltage Controlled Oscillator, | en |
dc.relation.page | 79 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2007-07-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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