一個24GHz的Doherty功率放大器

Abstract

本篇論文提出了兩個電路,一個是Doherty 功率放大器,另外一個是變壓器耦合全差動功率放大器.兩個都是操作在24 千兆赫茲.儘管Doherty 功率放大器已經被廣泛的討論過,但是對高頻的Doherty 功率放大器則相對缺乏.量測結果顯示出Doherty 功率放大器的電路架構很難在高頻的時候達到高的功率附加效率.這篇論文中的一級Doherty 功率放大器,使用台積電的130 奈米製程,量測到的功率增益是6.9 dB,輸出功率10 dBm, 量測到的頻寬是22.73 %,以及晶片大小是0.57mm².然而,量測到的功率附加效率只有8.3 %,這個一級的功率放大器在1.2 伏特的偏壓下消耗的電流是25 毫安培.為了達到更高的功率附加效率和功率增益,但不犧牲功率消耗的目標,這裡提出了一個交叉耦合電容的差動放大器,為了驗證此方法,一個差動電路和變壓器耦合全差動功率放大器電路一起設計用來比較,模擬結果證實了這個論點,使用一個相抵的技術的確可以提高穩定性,使用這種電路架構的一級功率放大器可以達到很突出的頻寬,69.6 %,在相同的偏壓下,模擬結果的功率增益是11.059 dB,功率附加效率是24.244 %.

This research proposes two circuits, one is a Doherty Power Amplifier (DPA), and the other one is a transformer-coupled fully differential power amplifier, both operating at 24 GHz. Although the DPA has been extensively investigated, the effects of DPA at high frequency DPA is still relatively unexplored. Test results, suggest it is hard to achieve high power-added-efficiency (PAE) using DPA construction at higher frequencies. A single-stage 24 GHz DPA fabricated in the TSMC 130-nm CMOS process presented in this thesis, has a measured gain of 6.9 dB, delivered output power is 10 dBm, measured bandwidth is 22.73 % and the chip area is 0.57 mm². However, measured PAE is only 8.3 %, and this single-stage PA consumes 25 mA from a bias voltage of 1.2V. In order to achieve higher PAE and gain without compromising power consumption, I intend to present a differential amplifier with cross-coupled capacitors. To verify this proposed method, a differential circuit and a transformer-coupled fully differential amplifier have been designed for comparison. A simulation test strongly supports the argument that using neutralization technique improves stability. A single-stage PA using this kind of circuit configuration obtains an outstanding bandwidth of 69.6 % vi with same supply voltage, simulated gain is 11.059 dB, PAE is 24.244 % .