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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24662完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平 | |
| dc.contributor.author | Zeng-Wen Chang | en |
| dc.contributor.author | 張正文 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:35:34Z | - |
| dc.date.copyright | 2005-01-31 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-01-27 | |
| dc.identifier.citation | [1]David A. Johns and Ken Martin, ”Analog Integrated Circuit Design,” John Wiley & Sons, Inc., 1997.
[2]Band-Sup Song, “CMOS A/D Converter Design,” Mixed-Signal Integrated Circuit Design Workshop, Section A, 2002. [3] Choi, M., Abidi, A.A, “A 6b 1.3GSample/s A/D converter in 0.35/spl mu/m CMOS” Solid-State Circuits Conference, Digest of Technical Papers. ISSCC. 2001 IEEE International, pp 126 –438, 2001 [4] B. S. Song, S. H. Lee, and M. F. Tompsett, “A 10-b 15-MHz COMS recycling two-step A/D converter,” IEEE J. Solid-State Circuits, vol. SC-25, pp. 1328-1337, Dec.1990. [5] A. G. F. Dingwall, and V. Zzzu, “A 8-MHz COMS subranging 8-bit A/D converter,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 1138-1143, Dec. 1985. [6] Bang-Sup Song, Seung-Hoon Lee, and Michael F. Tompsett, “A 10-b 15-MHz CMOS Recycling Two-Step A/D Converter” IEEE Journal of Solid-State Circuits, vol.25, No.6, pp 1328 –1337, Dec. 1990 [7] Toshihiko Shimizu, Masao Hotta, Kenji Maio, and Seiichi Ueda, “A 10-bit 20-MHz Two-Step Parallel A/D Converter with Internal S/H” IEEE Journal of Solid-State Circuits, vol.24, No.1, pp 13 –20, Dec. 1989 [8] Bram Nauta and Ardie G. W. Venes, “A 70-MS/s 110-mW 8-b CMOS Folding and Interpolation A/D Converter” IEEE Journal of Solid-State Circuits, vol.30, No.12,pp 1302 –1308, Dec. 1995 [9] K.-L. Lin, T. van den Boom, N. Stevanovic, J. Driesen, D. Hammerschmidt, and B.Hosticka, “A Basic Design Guide for CMOS Folding and Interpolating A/D Converters – Overview and Case Study” The 6th IEEE International Conference on Electronics, Circuits and Systems, Proceedings of ICECS '99, vol.1,pp529 –532, 1999 [10] R.J. Plassche, “Folding circuit for an analog-to-digital converter,” United States Patent 4,325,054, U.S. Philips Corporation, April 13, 1982. [11] R. V. D. Plassche, “Integrated Analog-to-Digital and Digital-to-Analog Converters,” Kluwer Academic Publishers, 1994. [12] Behazard Razavi, “Principles of Data Conversion Syatem Design”, IEEE PRESS, 1995. [13]P. Stulik, “Design issues in high speed, moderate resolution pipelined analog to digital converters,” Electrical Engineering of Washington State University, 1999. [14] Thomas Byunghak Cho, Paul R. Gray “A 10 b, 20 Msample/s, 35mW Pipeline A/D Converter” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp166~172, Mar. 1995 [15] Klaas Bult, Govert J. G. M. Geelen “ A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain” IEEE Journal of Solid-State Circuits, vol.25, No.6, pp 1379 –1384, Dec. 1990 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24662 | - |
| dc.description.abstract | 現今很多的應用像是無線通訊利用數位信號處理以便得到傳送的資訊. 因此在接收端和數位信號處理系統之間的類比數位轉換器是必要的. 隨著無線通訊系統爆炸性的成長, 低功率消耗及高速傳輸率變成越來越重要的問題. 因此本論文專注於研究低功率消耗及高速的類比數位轉換器. 在所有的互補式金屬氧化物半導體類比數位轉換器架構中, 導管式的架構可以在功率消耗及效能間取得一個良好的平衡.
在這論文中, 我設計了一個10位元、每秒五千五百萬取樣的類比數位轉換器. 這類比數位轉換器使用導管式的架構搭配數位錯誤修正以達到10位元的解析度. 這類比數位轉換器電路包含取樣維持電路、2位元快閃式類比數位轉換器、2位元數位類比轉換器、減法器、乘二電路、時脈產生器、編碼器、暫存器和數位錯誤修正電路. 模擬結果表示所設計的類比數位轉換器可達到每秒五千五百萬取樣率, 其差動非線性誤差及整體非線性誤差分別是±0.6LSB及±0.7LSB. 本論文中的類比數位轉換器使用台積電0.35um 2P4M n-well 互補式金屬氧化物半導體製程. 其輸入範圍為±1伏特. 在3.3伏特的電源供應下消耗功率為62毫瓦. 整體佈局面積為1100um × 1400um. | zh_TW |
| dc.description.abstract | Many of the applications nowadays utilize the digital signal processing to resolve the transmitted information like as wireless communication. Therefore, an analog-to-digital interface is required between the received terminal and the DSP system. With the explosive growth of wireless communication systems, Low power dissipation and high-speed transmission rate are becoming an increasingly important issue. Among many types of CMOS ADC architectures. A pipelined architecture can achieve good balance between power consumption and performance. This research focuses on low power dissipation and high speed ADC.
In this thesis, we design a 10-bit, and 55MSamples/s ADC. The ADC is implemented by a pipelined architecture with a resolution of 1.5-b/stage for digital error correction to obtain a 10-bit resolution at a sampling rate of 55MHz. The main sub-circuits of the ADC are sample-and-hold circuit, 2-bit flash A/D converter, 2-bit D/A converter, subtractor, multiply by two circuit, clock generator, encoder, register, and digital error correction. The sample-and-hold circuit is implemented with switched-capacitor techniques. The post-simulation results show that the overall circuit of ADC has 55MHz sampling rate, ±0.6LSB differential non-linearity, and ±0.7LSB integral non-linearity. The pipelined ADC is fabricated with TSMC 0.35µm 2P4M n-well CMOS technology. The input range of the ADC is ±1V. The chip dissipates 62mW from a 3.3V supply. Total layout area is 1100um × 1400um. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:35:34Z (GMT). No. of bitstreams: 1 ntu-94-R91943066-1.pdf: 6880181 bytes, checksum: a2ad98d7ec99a56012a4650460e996d6 (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | Abstract………………………………………………………...i
Table of Contents……………………………………………...ii List of Figures………………………………………………...iv List of Tables…………………………………………………vii CHAPTER 1. INTRODUCTION 1 1.1. MOTIVATION 1 1.2. THESIS ORGANIZATION 2 CHAPTER 2. ARCHITECTURE OF HIGH SPEED A/D CONVERTERS 3 2.1. INTRODUCTION 3 2.2. FULLY PARALLEL (FLASH) A/D CONVERTER 4 2.3. TWO-STEP A/D CONVERTER 5 2.4. FOLDING A/D CONVERTER 6 2.5. PIPELINE A/D CONVERTER 7 2.6. SUMMARY 8 CHAPTER 3. FUNDAMENTAL OF PIPELINE A/D CONVERTERS 10 3.1. ADC CHARACTERIZATION 10 3.1.1. Sampling Rate 10 3.1.2. Power Dissipation 11 3.1.3. Resolution 11 3.1.4. Input Capacitance 11 3.1.5. Input Swing 11 3.1.6. Input Bandwidth 12 3.1.7. Gain Error 12 3.2. ADC PERFORMANCE METRICS 12 3.2.1. SNR 13 3.2.2. DNL and INL 15 3.3. PRECISION OF THE S/H 16 3.4. PRECISION OF THE MDAC 17 3.5. SPEED OF THE S/H 18 3.6. TEN STAGE PIPELINE A/D CONVERTER 21 3.7. DIGITAL ERROR CORRECTION 22 CHAPTER 4. DESIGN OF THE 1.5B/STAGE PIPELINE A/D CONVERTER 27 4.1. BEHAVIORAL MODEL OF PIPELINE ADC USING THE SIMULINK 27 4.1.1. Behavioral Model of Sample-and-Hold circuit 28 4.1.2. One stage circuit 28 4.1.3. Final stage 2-bit flash ADC 29 4.1.4. 10-bit pipeline ADC 30 4.2. INPUT STAGE SAMPLE-AND-HOLD CIRCUITS 31 4.3. MULTIPLYING DAC 33 4.4. THE DESIGN OF OPERATIONAL TRANS-CONDUCTANCE AMPLIFIER 33 4.4.1. Low-Power High-Bandwidth OPAMP 37 4.5. DIFFERENTIAL DYNAMIC COMPARATORS 40 4.6. CLOCK GENERATOR 41 4.7. COMMON MODE FEEDBACK (CMFB) 42 4.8. FINAL 2-BIT ADC 43 CHAPTER 5. LAYOUT AND WHOLE CHIP SIMULATION 46 5.1. FLOOR PLANNING AND WHOLE CHIP LAYOUT 46 5.2. PRE-LAYOUT SIMULATION 46 5.3. INPUT FREQUENCY TEST IN POST-LAYOUT SIMULATION 48 5.4. SUMMARY 48 CHAPTER 6. CONCLUSIONS 50 6.1. CONCLUSIONS 50 6.2. FUTURE WORKS 50 REFERENCES 51 | |
| dc.language.iso | en | |
| dc.title | 55MS/s 10位元 導管式類比數位轉換器之設計 | zh_TW |
| dc.title | Design of a 55MS/s 10-Bit Analog to Digital Converter with Pipeline Architecture | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 顏志仁,鄭秋宏 | |
| dc.subject.keyword | 導管式類比數位轉換器, | zh_TW |
| dc.subject.keyword | Pipeline ADC, | en |
| dc.relation.page | 53 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2005-01-27 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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