互補式金氧半雙迴路頻率合成器之設計與實作

Abstract

近幾年，無線通訊的長足進步已逐漸取代有線傳輸成為現今最無可取代的通訊模式。急速成長的無線區域網路市場也極力的帶動高傳輸速率與傳輸量的需求。 在本論文裡，我們呈現了以無線通訊為取向，操作在2.4GHz頻帶，以雙迴路架構為基礎的頻率合成器。第一顆晶片包含相位頻率偵測器(PFD)，電荷幫浦(CP)，壓控振盪器(VCO)，混波器(Mixer)，以及多除數除法器。低通濾波器的部份由外接元件所實現。相較於傳統的整數位頻率合成器，此單晶雙迴路頻率合成器能在相位雜訊(phase noise)、頻道間隔(channel spacing)、參考頻率(reference frequency)和穩定延遲時間(settling time)之間取得較佳的取捨。 第二顆晶片也是以雙迴路為基礎。不同的是，其用來產生偏移頻率(offset frequency)的迴路，由直接數位頻率合成器(direct digital synthesizer)來取代。直接數位頻率合成器的使用，使得此頻率合成器能適用於直接頻率調變(direct frequency modulation)，而不需要使用在分數型頻率合成器用到的預強調(pre-emphasis)和數位校正迴路(digital calibration loop)等技巧。

Wireless communication has undergone an incredible development over last few years, and it's gradually replacing the cable communication to become the most important part of the modern world. The growing wireless LAN market has generated increasing interest in technologies enabling higher data rates and capacity than initially deployed systems. The dual-loop type frequency synthesizers for wireless applications are presented in this thesis. The first chip is composed of phase frequency detector (PFD), charge pump (CP), LC-tank voltage-controlled oscillator (VCO), and ring-type voltage-controlled oscillator, single-sideband mixer (SSB mixer), and multi-modulus driver. The required low-pass filter is provided by off-chip components in this design. The synthesizer employs a dual-loop architecture to realize a monolithic design with more optimal trade-off among phase noise, channel spacing, reference frequency and settling time compared to the conventional integer-N phase-locked loop architecture. The architecture of the second chip is based on dual-loop type synthesizer. However, the offset frequency is generated by a direct digital synthesizer. The use of the DDS makes this synthesizer potentially suitable for direct frequency modulation, without requiring any pre-emphasis and digital calibration loop that are instead necessary in fracional-N PLL.