請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24317完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李致毅(Jri Lee) | |
| dc.contributor.author | Da-Wei Chiu | en |
| dc.contributor.author | 邱大為 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:21:45Z | - |
| dc.date.copyright | 2005-07-29 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-26 | |
| dc.identifier.citation | [1] B. Razavi, Design of integrated Circuits for Optical Communication, 1st Ed., MxGraw-Hill, 2003.
[2] S. Haykin, Communication Systems, 4th Ed., John Wiley & Sons, 2001. [3] J. Winters and R. Gitlin, “Electric Signal Processing Techniques in Long-Haul Fiber Optical System,” IEEE Transaction on Communication, vol. 38, pp. 1439-1453, Sept. 1990. [4] J. N. Babanezhad, “A 3.3-V Analog Adaptive Line-Equalizer for Fast Ethernet Data Connection,” IEEE Custom Integrated Circuits Conference, pp. 343-346, May 1998. [5] G. P. Hartman, K. W. Martin and A. McLaren, “Continuous-Time Adaptive-Analog Coaxial Cable Equalizer in 0.5um CMOS,” IEEE ISCAS, pp. 97-100, May 1999. [6] G. Zhang, P. Chaudhari and M. M. Green, “A BiCMOS 10-Gb/s Adaptive Cable Equalizer,” IEEE Digest of International Solid-State Circuits Conference, pp. 482-483, Feb. 2004. [7] Y. Kudoh, M. Fukaishi and M. Mizuno, “A 0.13-μm CMOS 5-Gb/s 10-m 28AWG Cable Transceiver with No-feedback-loop Continuous-time Post-equalizer,” IEEE Journal Solid-State Circuits, vol. 38, pp. 741-746, May 2003. [8] J. Choi, M. Hwang and D. Jeong, “A 0.18um CMOS 3.5-Gb/s Continuous-time Adaptive Cable Equalizer Using Enhanced Low-frequency Gain Control Method,” IEEE Journal Solid-State Circuits, vol. 39, pp. 419-425, March 2004. [9] A. J. Baker, “An Adaptive Cable Equalizer for Serial Digital Video Rates to 400Mb/s,” IEEE Digest of International Solid-State Circuits Conference, pp. 174-175, Feb. 1996. [10] Y. Tomita, M. Kibune, J. Ogawa, W. W. Walker, H. Tamura and T. Kuroda, “A 10-Gb/s Receiver with Equalizer and On-chip ISI Monitor in 0.11-μm CMOS,” IEEE VLSI Circuits Symposium, pp. 202-205, Jun. 2004. [11] S. Gondi, J. Lee, D. Takeuchi and B. Razavi, “A 10-Gb/s CMOS Adaptive Equalizer for Backplane Applications,” IEEE Digest of International Solid-State Circuits Conference, pp. 328-329, Feb. 2005. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24317 | - |
| dc.description.abstract | 同軸電纜在高頻和長距離的資料傳輸中，由於其等效阻抗存在，而使訊號遭受其強度上的損失；此一損失量為訊號頻率的函數。為了彌補此一損失，我們通常利用一等化器將訊號重建增加其可信度。在此論文中，我將以類比電路的觀點，來設計一應用於同軸電纜Belden 8219的等化器，並利用一回授電路，使等化器能針對不同長度的同軸電纜來作補償。考量系統的整合性及低成本，我將使用0.18-μm CMOS 技術，因此在此論文中的電路將以TSMC 0.18-μm CMOS為基礎。 | zh_TW |
| dc.description.abstract | The data transmission of high-speed and long-distance coaxial cable suffers from magnitude losses due to its effective impedance, The loss is a function of signal frequency. To compensate the loss, we use an equalizer to rebuild the signal and increase its reliability. In this work, I would design an equalizer for the application of the Belden 8219 coaxial cable from an analog circuit point of view. It can also compensate various lengths of the cable via the adaptive control loop. Considering the system integration and low-cost requirement, I use 0.18-μm CMOS technology. Therefore, all circuit implementation in this work will base on TSMC 0.18-μm CMOS technology. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:21:45Z (GMT). No. of bitstreams: 1 ntu-94-R92943031-1.pdf: 1660471 bytes, checksum: 1aa2d8cea3229d95a5d340af0d6952b4 (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | Acknowledgements Ⅰ
Abstract Ⅲ Table of Contents Ⅴ List of Figures Ⅶ List of Tables Ⅹ Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Design Challenges and Research Goals 1 1.3 Thesis Outline 2 Chapter 2 Basic Concepts and System Overview 3 2.1 Basic Concepts 3 2.1.1 Random Binary Data 3 2.1.2 Eye Diagram 5 2.1.3 Bit Error Rate (BER) 8 2.2 Analysis of Transmission Line (Cable) 10 2.3 Cable Communication System 19 Chapter 3 Conventional Adaptive Cable Equalizer 21 3.1 Conventional Adaptive Cable Equalizer Architecture 21 3.2 Circuit Implementation 22 3.2.1 Equalizer Filter 22 3.2.2 Slicer 22 3.2.3 Rectifier 23 3.2.4 Error Amplifier 23 3.3 Conventional Adaptive Cable Equalizer problems 23 Chapter 4 Proposed Adaptive Cable Equalizer 27 4.1 Analysis of Equalization 27 4.1.1 Cable Characteristic 27 4.1.2 Equalizer Topology 32 4.1.3 Loop Analysis 34 4.2 Building Blocks 35 4.2.1 Equalizer Filter 35 4.2.2 Power Detector 40 4.2.3 Charge Pump 41 4.3 Layout View and Simulation Results 41 Chapter 5 Conclusions 47 References 49 | |
| dc.language.iso | en | |
| dc.title | 以0.18-μm CMOS製程製作之10-Gb/s等化器 | zh_TW |
| dc.title | A 10-Gb/s Adaptive Equalizer in 0.18-μm CMOS Technology | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),盧信嘉(Hsin-Chia Lu) | |
| dc.subject.keyword | 等化器, | zh_TW |
| dc.subject.keyword | adaptive,cable,equalizer, | en |
| dc.relation.page | 50 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2005-07-26 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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