半導體介面模擬及直通矽晶穿孔技術之應力分析

Abstract

半導體科技在製程微縮以提高元件性能及密度，傳統的二氧化矽層逐漸面臨漏電流增加的影響，為了使物理厚度增加以阻絕漏電流，業界改採用高介電常數閘極氧化層。當高介電常數閘極氧化層應用於半導體元件，由於其與二氧化矽介面不穩定，臨限電壓變得不容易控制，足以影響元件的特性。在本論文中我們利用第一原理計算的方法模擬當高介電常數氧化層與二氧化矽介面參入特定原子造成對臨限電壓的影響，並利用原子層沉積技術製作高介電常數氧化層電容元件以驗證模擬的結果。在二氧化矽(SiO2)與二氧化鉿(HfO2)中參入了鋁(Al)則臨限電壓往正的方向移動，而參入鑭(La)則臨限電壓往負移動。其造成臨限電壓移動的原因與參入原子之功函數有關，而與價數關係不大。 研究矽、鍺晶圓及其氧化層介面特性譬如氧化層的介面缺陷、固定電荷…等，我們通常使用電性量測的方法，如電荷泵(charge pump)。本論文中，我們使用了第一原理計算的方法解釋在介面上的缺陷對電性造成的影響。我們建立了多種超晶格結構，並分析介面上矽、鍺缺陷產生的懸鍵(dangling bond)對其能量在能帶圖中的位置。在矽與二氧化矽結構中，我們分析矽的懸鍵位能分別靠近價帶與傳導帶，在介面缺陷中分別扮演著給體(donor-like)、受體(acceptor-like)的角色。在鍺與其氧化層中也可看到不同懸鍵能量的分布位置，氧化數為零的鍺元素，其懸鍵的能量接近價帶，而氧化數越高，懸鍵能量則越接近傳導帶，理論上可解釋不同介面品質影響電荷捕捉之特性。 當半導體製程微縮技術面臨挑戰，新的結構或封裝方式成為了解決之道，3DIC便是未來可能的趨勢。3DIC是將不同晶片直接以矽晶穿孔技術連接起來，使得在相同面積下有多層的結構之概念。我們利用解析解求得矽晶穿孔填入銅後因熱應變所產生的效應，並與有限元素分析法相互比較。當相鄰的兩個矽晶穿孔受到熱應力，中間的平行方向會產生拉伸應變，而垂直方向會產生壓縮應變。而兩個矽晶穿孔的應力分析則會隨著彼此間距離漸小而與解析解有所差異，當距離過小解析解會大於有限元素分析的應變量。最後，我們做了立體結構的有限元素法計算，發現在表面所受到的應變比解析解來的高。因此我們訂定了表面修正參數以修正解析解。此表面修正參數與有限元素分析中矽基板的厚度無關，所以可以適用到任何厚度之矽晶穿孔通道。此應力模擬可做為未來3DIC設計參考，在受到拉伸應變的區域置入n-FET，或是利用此應力特性使得p-FET及n-FET取得更好的平衡。

As the scaling of semiconductor industry continues, the performance and density of device grow. The traditional silicon dioxide has met the problem of leakage current. In order to reduce the leakage current and increase the physical thickness we use high-k materials as gate dielectric. But because of the instability between High-k and native oxide, it is not easy to control the threshold voltage, and this affect the performance of devices. In this thesis, we use first principle calculation to simulate the affect to threshold voltage when we introduce some dopant into the interface of High-k layer and SiO2. When we doped Al at the interface of SiO2/HfO2, the threshold voltage shifted positively. On the contrary, if we doped La at the interface, the threshold voltage will shift negatively. It is the work function of the doped element that affects the threshold voltage, not the valence charges. In order to obtain the interface property like interface trap, we often use charge pumping, or conductance method. In this thesis, we use first principle calculation method to explain how the defect at interface affects the electric property. We build different kinds of SiO2/Si and GeO2/Ge structures, and analysis the Silicon, Germanium dangling bond’s energy level at bandgap. In SiO2/Si interface, the defect level near valence band is call donor-like defect, and the defect level near conduction band is the acceptor-like defect. In GeO2/Ge model, we can see different energy distribution of the Ge dangling bond. For Ge+0 (Ge dangling bond), the defect level is near valence band. And defect level will close to conduction band when the oxidation number of Ge is higher. The result can explain different characteristic in charge trapping. When scaling of device faces challenge, a new structure or package can become the solution. 3D IC is more and more important. It can be used to place different chip together with through silicon via (TSV), and different function can be integrated in single area. We here use analytical solution to find out the strain effect when silicon with TSV is cooling down from higher temperature, and compared with finite element calculation. When 2 TSV are close together, the area between TSVs will suffer from tensile strain in horizontal direction and compressive strain in vertical direction. The analytical solution will different from FEM result when TSVs are too close, and analytical solution will overestimate the strain between TSVs. When we do the FEM in 3D model and the surface will have more strain than analytical solution. We set a surface correction factor Cw to fix analytical solution. Cw is independent from thickness of silicon model, so it can fit to any thickness of TSV model. This analysis can be used as a design rule to increase carrier mobility in n-FET or p-FET.