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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Cheng-Feng Chung | en |
| dc.contributor.author | 鍾政峰 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:16:12Z | - |
| dc.date.copyright | 2006-02-07 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-01-26 | |
| dc.identifier.citation | [1] B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press,1995.
[2] David A. Johns and Ken Martin, “Analog Integrated Circuit Design,” John Wiley & Sons Inc, 1997. [3]Rudy J. Van de Plassche, “CMOS Intergrated Analog-to-Digital and Digital-to-Analog Converter,” Kluwer Academic Publishers, 2004 [4] A. Van den Bosch, M.A.F. Borremans, M.S.J. Steyaert, and W. Sansen, “A 10‐bit1‐GSample/s Nyquist current‐steering CMOS D/A converter,” IEEE J.Solid‐State Circuits, vol. 36, no. 3, pp. 315‐324, Mar. 2001. [5] C.H. Lin and K. Bult, “A 10‐b, 500‐MSample/s CMOS DAC in 0.6 mm2,” IEEE J.Solid‐State Circuits, vol. 33, no. 12, pp. 1948‐1958, Dec. 1998. [6] M. J. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid‐State Circuits, vol. 24, pp. 1433‐1440, Oct.1989. [7] J. Bastos, A.M Marques, M.S.J. Steyaert, and W. Sansen, ”A 12‐bit intrinsic accuracy high speed CMOS D/A converter,” IEEE J. Solid‐State Circuits, vol. 33, no. 12, pp. 1959‐1969, Dec. 1998. [8] Paul R Gray and Robert G. Meyer, “Analysis and Design of Analog Integrated Circuits,”John Wiley & Sons, 1993. [9] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, “A 10-b 70-MS/s CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 26,no. 4, pp. 637–642, Apr. 1991. [10] J. Bastos, M. Steyaert, A. Pergoot, and W. Sansen, “Influence of die attachment on MOS transistor matching,” IEEE Trans. Semiconduct. Manufact., pp. 209–217, May 1997. [11] G. Van Der Plas, J. Vandenbussche, W. Sansen, M. Steyaert, and G.Gielen, “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC,”IEEE J. Solid-State Circuits, vol. 34, pp. 1708–1717, Dec. 1999. [12] J. Vandenbussche and G. Van den Bosch et al., “A 14-bit 100-MSamples update rate Q2 random-walk CMOSD/A converter,” in Proc. IEEE 1999 Int. Solid State Circuits Conf. (ISSCC), Feb. 1999, pp. 146–147. [13] A. Van den Bosch and M. Borremans et al., “A 12-bit 200-MHz lowglitch CMOS D/A converter,” in IEEE 1998 Custom Integrated Circuits Conf. (CICC), May 1998, pp. 249–252. [14] Y. Cong and R. L. Geiger, “Switching-sequence optimization for gradient error-compensation in thermometer-decoded DAC array,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 585–595, July 2000. [15] S.Y. Chin and C. Y. Wu, “A 10‐b 125‐MHz CMOS digital‐to‐analog converter with threshold‐voltage compensated current sources,” IEEE J. Solid‐State Circuits, vol. 29, no .11, pp. 1374‐1380, Dec. 1994. [16] J. Bastos, M.S.J. Steyaert, and W. Sansen, “A high yield 12‐bit CMOS D/A converter,” in Proc. IEEE 1996 CICC, pp. 20.6.1‐20.6.4, May 1996 [17] A. Van den Bosch, M.S.J. Steyaert, and W. Sansen, “SFDR‐bandwidth limitations for high‐speed high resolution current‐steering CMOS D/A converters,” in Proc. IEEE Int. Conf. Electronics, Circuits and Systems (ICECS),Sept. 1999, pp. 1193‐1196. [18] A. R. Bugeja and B. S. Song, “A self‐trimming 14‐b 100MS/s CMOS DAC,”IEEE Journal of Solid‐State Circuits, vol. 35, pp.1841‐1852, Dec. 2000. [19] P.Hendriks, “Specifying communication DAC’s.” IEEE Spectrum, pp. 58-69, July 1997 [20] T. Wu, C. Jih, J. Chen, and C. Wu, “A low glitch 10-bit 75-MHz CMOS video D/A Converter,” IEEE J. Solid-State Circuits, vol. 30, no. 1, pp. 68-72, Jan. 1995. [21] J. Fournier and P. Senn, “A 130 MHz 8-bit CMOS video DAC for HDTV applications,” IEEE J. Solid-State Circuits, vol. 26 no. 7, pp. 1073-1077, July 1991. [22] A. Cremonesi, F. Maloberti, and G.. Polito, “A 100-MHz CMOS DAC for video-graphic systems,” IEEE J. Solid-State Circuits, vol. 24, no. 3, pp. 635-639,June 1989. [23] Mikael Gustavsson, J.Jacob Wikner, and Nianxiong Nick Tan, “CMOS data converters for communications,” Boston, 2000. [24] Hiroyuki Kohno, Yasuyuki Nakamura, Atsuhito Kondo, Hiroyuki Amishiro,Takahiro Miki, Keisuke Okada, ”A 350‐MS/s 3.3V 8‐bit CMOS D/A converter using a delayed driving scheme,” IEEE CICC, pp. 10.5.1‐10.5.4 [25] T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, “An 80-MHz 8-bit CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. SSC-21, p. 983 988, Dec. 1986. [26] Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2001 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24112 | - |
| dc.description.abstract | 這篇論文提出了一個十位元250百萬赫茲的電流切換式數位類比轉換器，它使用的是雙倍區段化的架構，其中包含了五位元的高位元，中間兩位元的高位元以及最後用來當成控制二進制電流源的三位元。這樣的設計不僅可以保持原本電流切換式架構的優點，更可以達到降低功率消耗的好處。在這篇論文中我們實現了兩種數位類比轉換器，一個是使用二維切換方式，另一種是使用我們所提出的切換方式來實現。這個新的切換方式是將高位元的電流源分成八個部份來補償拋物線誤差並且使用數狀圖來達到最佳化的目的。
這個數位類比轉換器是使用UMC 0.18微米混合信號互補式金氧半製程來實現。它的差動非線性失真及整體非線性失真分別為0.2LSB及0.7LSB。當操作在200百萬赫茲及輸入頻率為1百萬赫茲時，SFDR達到64dB。功率消耗在1.8伏特操作之下為20毫瓦。整體晶片的核心面積為0.72x0.68mm2 。 | zh_TW |
| dc.description.abstract | This thesis proposes a 10 bit 250MHz current steering DAC with a doubly segmented current steering architecture that consists of two parts: upper 5 bit MSBs and intermediate 2 bit MSBs. The other 3 bit LSBs are binary weighted current source. This design not only keeps the advantages of current steering architecture, but also consumes lower power. Two types of DACs are implemented. One is implemented by a two-dimension switching scheme, another one is implemented by the proposed switching scheme. The new switching scheme divides the MSB current source into eight parts to compensate parabolic error and also use tree structure to optimize.
This DAC is to be implemented with a UMC 0.18 µm 1P6M mixed signal CMOS process. The DNL and INL are 0.2 and 0.7 LSB, respectively. The SFDR is 64dB when the update rate is 200MHz and the input frequency is 1MHz. The power consumption is 20 mW, and it operates from 1.8V. The active area is 0.72x0.68mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:16:12Z (GMT). No. of bitstreams: 1 ntu-95-R92943086-1.pdf: 2131868 bytes, checksum: 3d8f03374727b1025ee72a4aff445e25 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | 摘要.................................................i
Abstract.............................................ii Table of Contents....................................iii List of Figures.......................................v List of Tables.......................................vii Chapter1 Introduction..................................1 1.1 Motivation....................................1 1.2 Thesis Organization...........................2 Chapter 2 Fundamentals of Digital-to-Analog Converter..3 2.1 Introduce of Digital-to-Analog Converter......3 2.2 Static Performance............................5 2.3 Dynamic Performance...........................6 2.4 Digital-to-Analog Converter Architecture......9 2.4.1 Resistor DAC Architecture.....................9 2.4.2 Charge Redistribution DAC....................10 2.4.3 R-2R Current DAC.............................11 2.4.4 Current Steering DAC.........................12 Chapter 3 Implementation of Current Steering DAC......16 3.1 Basic Segmented Current Steering DAC Architecture..........................................16 3.2 Segmentation of Current Steering DAC.........17 3.3 Finite Output Impedance of Current Source....21 3.4 Current Source Mismatch......................24 3.4.1 Random Error.................................24 3.4.2 Systematic Error.............................28 3.5 Bias Circuit.................................29 3.6 Digital Circuit..............................30 3.6.1 Thermometer Decoder..........................30 3.6.2 Latch Design.................................32 3.6.3 Clock Distribution...........................34 3.7 Layout Consideration.........................34 3.8 Simulation Results...........................35 3.8.1 Static Simulation............................36 3.8.2 Settling Time Simulation.....................36 3.8.3 FFT Simulation...............................37 3.9 Summary......................................37 Chapter 4 The Proposed New Switching Scheme to Compensate Parabolic Error.......................................39 4.1 Systematic Error in Current Steering DAC.....39 4.2 Two Dimension Centroid Switching Scheme......40 4.3 The Proposed New Switching Scheme to Compensate Parabolic Error.......................................41 Chapter 5 Test Setup and Experimental Results.........47 5.1 Test Setup...................................47 5.1.1 Static Test..................................47 5.1.2 Dynamic Test.................................48 5.2 Experimental Results.........................52 5.2.1 Static Test..................................54 5.2.2 Dynamic Test.................................56 5.3 Summary......................................62 Chapter 6 Conclusion and Futrue Work..................65 6.1 Conclusion...................................65 6.2 Future Work..................................66 Biliography...........................................67 | |
| dc.language.iso | zh-TW | |
| dc.subject | 十位元 | zh_TW |
| dc.subject | 數位類比轉換器 | zh_TW |
| dc.subject | 電流切換式 | zh_TW |
| dc.subject | dac | en |
| dc.subject | 10 bit | en |
| dc.subject | current steering | en |
| dc.title | 一個具有新切換方式補償拋物線誤差之10位元互補式金氧半電流切換式數位類比轉換器 | zh_TW |
| dc.title | A new switching scheme for parabolic error compensation in 10 bit CMOS current steering digital to analog converter | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 洪士灝,楊世宗 | |
| dc.subject.keyword | 數位類比轉換器,電流切換式,十位元, | zh_TW |
| dc.subject.keyword | dac,current steering,10 bit, | en |
| dc.relation.page | 68 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2006-01-26 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-95-1.pdf 未授權公開取用 | 2.08 MB | Adobe PDF |
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