請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24005完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李致毅(Jri Lee) | |
| dc.contributor.author | Jian-Yu Ding | en |
| dc.contributor.author | 丁建裕 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:13:54Z | - |
| dc.date.copyright | 2006-07-12 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-10 | |
| dc.identifier.citation | Bibliography
[1] M. Choi and A. A. Abidi, “A 6-b 1.3-Gsample/s A/D Converter in 0.35-μm CMOS,” IEEE J. Solid-State Circuits, vol. 36, pp. 1847-1858, Dec. 2001. [2] Jaesik Lee et al., “A 5-b 10-GSample/s A/D Converter for 10-Gb/s Optical Receivers,” IEEE J. Solid-State Circuits, vol. 39, pp. 1671-1679, Oct. 2004. [3] A. G. W. Venes and R. J. van de Plassche, “An 80-MHz, 80-mW, 8-b CMOS Folding A/D Converter with Distributed Track-and-Hold Preprocessing,” IEEE J. Solid-State Circuits, vol. 31, pp. 1846-1853, Dec. 1996. [4] P. C. S. Scholtens and M. Vertregt, “A 6-b 1.6-Gsample/s Flash ADC in 0.18-μm CMOS Using Averaging Termination,” IEEE J. Solid-State Circuits, vol. 37, pp. 1599-1609, Dec. 2002. [5] M. Shinagawa et al., “Jitter Analysis of High-Speed Sampling Systems,” IEEE J. Solid-State Circuits, vol. SC-25, pp. 220-224, Feb. 1990. [6] H. Pan et al., “A 3.3-V 12-b 50-MS/s A/D Converter in 0.6-μm CMOS with over 80-dB SFDR,” IEEE J. Solid-State Circuits, vol. 35, pp. 1769-1780, Dec. 2000. [7] E. M. Cherry and D. E. Hooper, “The Design of Wideband Transistor Feedback Amplifiers,” Proc. IEE, vol. 110, pp. 375-389, Feb. 1963. [8] Jri Lee and Behzad Razavi, “A 40-Gb/s Clock and Data Recovery Circuit in 0.18-μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 38, pp. 2181-2190, Dec. 2003. [9] B. Razavi, Principles of Data Conversion System Design. Piscataway, NJ: IEEE PRESS, 1995. [10] C. Paulus et al., “A 4GS/s 6b Flash ADC in 0.13μm CMOS,” Digest of Symposium on VLSI Circuits, pp. 420-423, June 2004. [11] Jaeski Lee et al, “A 5-b 10-GSample/s A/D Converter for 10-Gb/s Optical Receivers,” IEEE J. Solid-State Circuits, vol. 39, pp. 1671-1679, Oct. 2004. [12] Christoph Sandner,et al, “A 6-bit 1.2-GS/s Low-Power Flash-ADC in 0.13-μm Digital CMOS,” IEEE J. Solid-State Circuits, vol. 40, pp. 1499-1505, July 2005. [13] S. K. Tewksbury, et al., “Terminology Related to the Performance of S/H, A/D, and D/A circuits”, IEEE Trans. Circuits Syst., vol. CAS-25, pp. 419-426, July 1978. [14] Nicholas Gray, “ABCs of ADCs,” National Semiconductor Corporation, 2003. [15] H. Pan, “A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over 80-dB SFDR,” Ph.D. dissertation, Univ. of California, Los Angeles, CA, Dec. 1999. [16] David Johns and Ken Martin, “Analog Integrated Circuit Design,” Published by John Wiley & Sons, Inc., 1997. [17] Mikael Gustavsson, Jacob Wikner, and Nianxiong Nick Tan, “CMOS Data Converters for Communications” Kluwer Academic Publiser, 2000. [18] William Cheng et al., “3-b GS/s ADC-DAC in μm SiGe Technology,” ISSCC Dig. Tech. Papers, pp. 262-263, Feb. 2004. [19] Yuko Tamb, et. al., “A CMOS 6b 500MSample/s ADC for a Hard Disk Drive Read Channel,” ISSCC Dig. Tech. Papers, pp. 324-325, Feb. 1999. [20] Kwangho Yoon, et. Al., “A 6b 500MSample/s CMOS Flash ADC with a Background Interpolated Auto-Zeroing Technique,” ISSCC Dig. Tech. Papers, pp. 326-327, Feb. 1999. [21] Klaas Bult and Aaron Buchwald, “An Embadded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2,” IEEE J. Solid-State Circuits, vol. 32, pp. 1887-1895, Dec. 1997. [22] Ardie G. W. Venes and Ruby J. van de Plassche, “An 80-mW 8-b CMOS Folding A/D Converter with Distributed Track-and-Hold Preprocessing,” IEEE J. Solid-State Circuits, vol. 31, pp. 1841-1853, Dec. 1996. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24005 | - |
| dc.description.abstract | 隨著數位應用及信號系統的大量增加，市場對於高速類比/數位轉換器的需求與日俱增。其中快閃式架構的類比/數位轉換器，適用於以高速要求為主，並且不需要高解析度的應用。舉例而言, 硬碟驅動系統的讀寫，通訊系統， 微波電子天文望遠鏡，以及每秒十億取樣的微波接收器，都屬於此應用範圍。
我們提出了一個五位元，每秒十億次取樣的類比/數位轉換器。其採用了分散式取樣，並且以數位補償製程不匹配所產生的偏差電壓。取樣的方式，是以電流模式的正反器(current-mode flipflops)來實現，由於取消了訊號路徑上的開關，故可避免來自於輸入訊號變化造成失真。我們以五位元的數位方式做校正偏差電壓。此轉換器是以0.18-μm金氧半電晶體製程製做，其差動及積分非線性失真分別是0.4及0.6 LSB。在10 GHz的取樣頻率下，其有效位數為4.05位元。本電路類比部份使用1.8伏特的電壓，包括時脈緩衝級的消耗功率為 560 mW 。晶片總面積為1.58 mm × 1.11 mm。 | zh_TW |
| dc.description.abstract | With the increasing use of digital computing and signal processing, the need of high-speed ADCs increases with time. Flash ADCs are still the architecture of choice, where maximum sampling rate and need no high resolution. For example, read-write channel of a disk drive systems, communication systems, microwave telescope array, and 10-GSamples/s microwave receiver are the cases.
A 5-b 10-GSample/s analog-to-digital converter incorporates distributed sampling and digital offset calibration techniques. The sampling is accomplished by current-mode flipflops, eliminating the input-dependent distortions. The offset is calibrated digitally with a resolution of 5 bits. Fabricated in 0.18-μm CMOS technology, this converter achieves differential and integral nonlinearities of 0.4 and 0.6 LSB, respectively, and 4.05 effective bits at a sampling rate of 10 GHz. The circuit consumes 560 mW from a 1.8-V supply and occupies an area of 1.58 mm × 1.11 mm including pads. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:13:54Z (GMT). No. of bitstreams: 1 ntu-95-R93943007-1.pdf: 3247434 bytes, checksum: 6faa3fd15c607e7a4affd9e1fb4132cc (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | Contents
Chapter 1 Introduction..............................................1 1.1 Motivation................................................1 1.2 Thesis Organization.......................................2 Chapter 2 Fundamental of Analog-to-Digital Converters...............3 2.1 Performance Metrics...................................3 2.1.1 Resolution..........................................3 2.1.2 Sampling Rate.......................................3 2.1.3 DNL and INL.........................................4 2.1.4 SNR, THD, and SNDR..................................5 2.1.4 ENOB................................................8 2.2 Architectures for High-Speed A/D Converters...........9 2.2.1 Flash A/D Converter.................................9 2.2.2 Two-Step A/D Converter.............................11 2.2.3 Folding A/D Converter..............................11 2.2.4 Pipeline A/D Converter.............................13 2.3 Summary..............................................14 Chapter 3 Design of the 5-bit 10GS/s Analog-to-Digital Converter...15 3.1. Introduction........................................16 3.2. ADC ARCHITECTURE....................................16 3.2.1. Distributed Sampling..............................18 3.2.2 Offset Calibration.................................22 3.3. BUILDING BLOCKS.....................................27 3.3.1. Preamplifier......................................27 3.3.2 Flipflop...........................................30 3.3.3. Clock Buffer......................................31 3.3.4 Testing DAC........................................32 Chapter 4 Simulation, Layout, and Measurement Results.............34 4.1 Simulation and Layout................................34 4.1.1 Transient Simulation and Layout....................34 4.1.2 Monte-Carlo Simulation.............................37 4.2 Measurement Results..................................41 4.2.1 Statistic Testing..................................43 4.2.2 Dynamic Testing....................................48 4.3 Performance Summary..................................53 Chapter 5 Conclusions..............................................54 5.1Conclusions...........................................54 Bibliography.............................................55 | |
| dc.language.iso | en | |
| dc.subject | 偏差校正 | zh_TW |
| dc.subject | 類比/數位轉換器 | zh_TW |
| dc.subject | 分散式取樣 | zh_TW |
| dc.subject | 直接ADC-DAC測試 | zh_TW |
| dc.subject | A/D converter | en |
| dc.subject | direct ADC-DAC test. | en |
| dc.subject | offset calibration | en |
| dc.subject | distributed sampling | en |
| dc.title | 5位元10GS/s類比/數位轉換器-以0.18-μm CMOS製程製作 | zh_TW |
| dc.title | A 5-bit 10-GSample/s A/D Converter in 0.18-μm CMOS Technology | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),盧信嘉(Hsin-Chia Lu) | |
| dc.subject.keyword | 類比/數位轉換器,分散式取樣,偏差校正,直接ADC-DAC測試, | zh_TW |
| dc.subject.keyword | A/D converter,distributed sampling,offset calibration,direct ADC-DAC test., | en |
| dc.relation.page | 56 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2006-07-11 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-95-1.pdf 未授權公開取用 | 3.17 MB | Adobe PDF |
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