V頻帶低雜訊主動差動訊號匹配器與W頻帶峰值檢測器之設計與實現

Abstract

本論文的研究著重於六百億赫茲短距離傳輸與被動式毫米波影像的應用，兩者皆需要將毫米波電路的高頻效應融入於設計中，並透過電磁模擬去觀察是否達到預期的設計目標，因此本論文將對於COMOS電路在高頻應用中參數的設計與選取做討論，並且將應用在高頻的被動元件的設計考量融入整體的討論中。 V-band低雜訊主動差動訊號匹配器的設計結合了低雜訊放大器與平衡非平衡匹配器，進而可以在接收機前端將單一相位的訊號轉換成差動訊號，使系統在線性度與雜訊上有較好的表現，所提出的電路運用電路架構去修正平衡非平衡匹配器在高頻所產生的相位誤差，進而提供一個較不受製程變異與模擬誤差影響的電路。此電路的量測到的頻寬為60.4-66.6 GHz，頻寬內所量測到的最大電壓增益為17.6 dB與16 dB (63 GHz)，頻寬內的相位誤差皆小於6.8度而增益誤差皆小於1.7 dB，最低雜訊指數(noise figure)為8.6 dB (63 GHz), 整體電路消耗19 mW的功率，晶片的核心面積為0.275 mm2. W-band功率偵測器的運作是將75 GHz至110 GHz的高頻訊號接收至電路中並且將所收到的功率大小表現在輸出的直流電壓變化上，本次設計的晶片將電晶體操作在線性區以達成降低等效雜訊功率的目標。本次晶片所量測到的S11在75 GHz至110 GHz內皆達到小於-10 dB的要求，功率大小轉換至直流變化的能力由responsivity表示，所量測到的responsivity為1.77 kV/W, 量測到的等效雜訊功率(NEP)約為17 pW/(Hz)^0.5,電路消耗的總功率為0.18 mW而晶片面積為0.163 mm2。

This thesis presents the researches for 60 GHz short range wireless system and millimeter-wave passive imaging applications. The high frequency effects in both designs need to be considered and observed through electromagnetic simulation. This thesis will focus on the design of CMOS circuits operating at high frequency and put the design considerations for passive components into discussion. The V-band low-noise active balun combines a low-noise amplifier and an active balun circuit, so the signal can be amplified and converted from single to differential at front-end. The proposed circuit calibrates the phase error of active balun through circuit structure and provides a robust calibration technique for millimeter-wave application. The chip is fabricated in 90 nm low power CMOS technology and occupies an active area of 0.275 mm2. The 3 dB bandwidth is from 60.4-66.6 GHz, the maximum equivalent voltage gain is 17.6 dB and the minimum noise figure is 8.6 dB. The power consumption is only 19 mW from a 1.4 V supply voltage. The measured phase error maintains less than 6.8˚ within 3 dB bandwidth and keeps below 10˚ within 50-67 GHz. The W-band power detector receives the signal from 75 GHz to 110 GHz and converts the power level into the change of DC voltage. The transistor of this work operates at linear region to improve the performance of noise-equivalent power. The chip is fabricated by 65 nm CMOS technology and the chip area is 0.163 mm2. The power consumption is 0.18 mW and the supply voltage is 1V. The measured input reflection coefficient is less than -10 dB within W-band frequency. The measured average responsivity is designed to achieve 1.77k while the measured NEP with average responsivity is about 17 pW/(Hz)^0.5.